[PATCH] D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions

[luxufan via Phabricator via llvm-commits]

StephenFan updated this revision to Diff 285589.
StephenFan added a comment.

Remove sumop, Remove MOPSTIndexedOrder. zvlsseg -> FeatureStdExtV


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84416/new/

https://reviews.llvm.org/D84416

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVSchedRocket32.td
  llvm/lib/Target/RISCV/RISCVSchedRocket64.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/rvv/zvlsseg.s

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