[llvm] 2632c62 - [ARM] Mark VMINNMA/VMAXNMA as commutative
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 13 10:01:35 PDT 2020
Author: David Green
Date: 2020-08-13T18:01:11+01:00
New Revision: 2632c625ed9b7cb5d384242e9a792a8c5703fda4
URL: https://github.com/llvm/llvm-project/commit/2632c625ed9b7cb5d384242e9a792a8c5703fda4
DIFF: https://github.com/llvm/llvm-project/commit/2632c625ed9b7cb5d384242e9a792a8c5703fda4.diff
LOG: [ARM] Mark VMINNMA/VMAXNMA as commutative
These operations take Qda and Rn register operands, which are
commutative so long as the instruction is not predicated.
Differential Revision: https://reviews.llvm.org/D85813
Added:
Modified:
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.h
llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 48b8d44cacfd..c4ce13677b30 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4055,6 +4055,8 @@ class MVE_VMAXMINNMA<string iname, string suffix, bit size, bit bit_12,
let Inst{4} = 0b0;
let Inst{3-1} = Qm{2-0};
let Inst{0} = 0b1;
+
+ let isCommutable = 1;
}
multiclass MVE_VMAXMINNMA_m<string iname, MVEVectorVTInfo VTI,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 43942316b80e..d728572e2858 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -258,6 +258,22 @@ void Thumb2InstrInfo::expandLoadStackGuard(
expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
}
+MachineInstr *Thumb2InstrInfo::commuteInstructionImpl(MachineInstr &MI,
+ bool NewMI,
+ unsigned OpIdx1,
+ unsigned OpIdx2) const {
+ switch (MI.getOpcode()) {
+ case ARM::MVE_VMAXNMAf16:
+ case ARM::MVE_VMAXNMAf32:
+ case ARM::MVE_VMINNMAf16:
+ case ARM::MVE_VMINNMAf32:
+ // Don't allow predicated instructions to be commuted.
+ if (getVPTInstrPredicate(MI) != ARMVCC::None)
+ return nullptr;
+ }
+ return ARMBaseInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
+}
+
void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
const DebugLoc &dl, Register DestReg,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index e31c49a38959..808167bfdcbc 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -64,6 +64,10 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
SmallPtrSetImpl<MachineInstr *> &SeenMIs,
bool) const override;
+ MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
+ unsigned OpIdx1,
+ unsigned OpIdx2) const override;
+
private:
void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
};
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll b/llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
index 72576c8d8adc..6a30d964392a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
@@ -17,8 +17,7 @@ define arm_aapcs_vfpcc <4 x float> @maxf32(<4 x float> %a, <4 x float> %b) {
define arm_aapcs_vfpcc <4 x float> @maxf32_c(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: maxf32_c:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxnma.f32 q1, q0
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmaxnma.f32 q0, q1
; CHECK-NEXT: bx lr
%aa = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
%bb = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
@@ -40,8 +39,7 @@ define arm_aapcs_vfpcc <4 x float> @minf32(<4 x float> %a, <4 x float> %b) {
define arm_aapcs_vfpcc <4 x float> @minf32_c(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: minf32_c:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminnma.f32 q1, q0
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vminnma.f32 q0, q1
; CHECK-NEXT: bx lr
%aa = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
%bb = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
@@ -114,8 +112,7 @@ define arm_aapcs_vfpcc <8 x half> @maxf16(<8 x half> %a, <8 x half> %b) {
define arm_aapcs_vfpcc <8 x half> @maxf16_c(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: maxf16_c:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxnma.f16 q1, q0
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vmaxnma.f16 q0, q1
; CHECK-NEXT: bx lr
%aa = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
%bb = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
@@ -137,8 +134,7 @@ define arm_aapcs_vfpcc <8 x half> @minf16(<8 x half> %a, <8 x half> %b) {
define arm_aapcs_vfpcc <8 x half> @minf16_c(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: minf16_c:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminnma.f16 q1, q0
-; CHECK-NEXT: vmov q0, q1
+; CHECK-NEXT: vminnma.f16 q0, q1
; CHECK-NEXT: bx lr
%aa = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
%bb = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
@@ -254,11 +250,10 @@ define void @loop_absmax32_c(float* nocapture readonly %0, i32 %1, float* nocapt
; CHECK-NEXT: lsr.w lr, r1, #3
; CHECK-NEXT: wls lr, lr, .LBB17_3
; CHECK-NEXT: @ %bb.1: @ %.preheader
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: .LBB17_2: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrw.u32 q0, [r0], #16
+; CHECK-NEXT: vldrw.u32 q1, [r0], #16
; CHECK-NEXT: vmaxnma.f32 q0, q1
-; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: le lr, .LBB17_2
; CHECK-NEXT: .LBB17_3:
; CHECK-NEXT: vldr s4, .LCPI17_0
@@ -447,11 +442,10 @@ define void @loop_absmax16_c(half* nocapture readonly %0, i32 %1, half* nocaptur
; CHECK-NEXT: lsr.w lr, r1, #3
; CHECK-NEXT: wls lr, lr, .LBB21_3
; CHECK-NEXT: @ %bb.1: @ %.preheader
-; CHECK-NEXT: vmov.i32 q1, #0x0
+; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: .LBB21_2: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vldrw.u32 q0, [r0], #8
+; CHECK-NEXT: vldrw.u32 q1, [r0], #8
; CHECK-NEXT: vmaxnma.f16 q0, q1
-; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: le lr, .LBB21_2
; CHECK-NEXT: .LBB21_3:
; CHECK-NEXT: vldr.16 s4, .LCPI21_0
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