[PATCH] D84360: [LLD][PowerPC] Implement GOT to PC-Rel relaxation
Stefan Pintilie via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 12 14:35:41 PDT 2020
stefanp accepted this revision as: stefanp.
stefanp added a comment.
This revision is now accepted and ready to land.
This patch makes sense to me.
I have a question about the access instruction but I don't think we should worry about it now.
LGTM!
================
Comment at: lld/ELF/Arch/PPC64.cpp:533
+// paddi 3, 0, 1000, 1
+// lwz 3, 20(3)
+// Should add up to 1020 for total displacement.
----------------
Is it possible to have:
```
paddi 3, 0, 1000, 1
plwz 3, 20(2)
```
Where both instructions are prefixed.
I assume probably not (clang won't generate it?) but I figured it is worth asking.
================
Comment at: lld/ELF/Arch/PPC64.cpp:682
+ "unrecognized instruction for R_PPC64_PCREL_OPT relaxation: 0x" +
+ Twine::utohexstr(accessInsn));
+ break;
----------------
I guess if the access instruction is already a prefixed instruction there won't be an equivalent PC Relative form of it and we will produce an error here.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D84360/new/
https://reviews.llvm.org/D84360
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