[PATCH] D85724: [SVE] Lower fixed length vector integer shifts.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

I can confirm the shift-by-immediate cases don't result in optimal code generation.  This is because the current AArch64lsl_p patterns are linked to the unpredicated instructions which explicitly check for an all 1s predicate.  I'll fix this up under a separate patch because it might affect the scalable side, which is probably where it's best tested given the fixed length lowering doesn't care about immediates.  This is why I'm keen for the fixed-length and scalable lowering to target the same nodes so that fixed-length does not introduce any new isel requirements.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85724/new/

https://reviews.llvm.org/D85724