[PATCH] D82603: AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D82603#2173645 <https://reviews.llvm.org/D82603#2173645>, @cfang wrote:

> In D82603#2119746 <https://reviews.llvm.org/D82603#2119746>, @nhaehnle wrote:
>
>> Could you make this generic over the VGPR register class instead? That code duplication is rather annoying.
>
> I agree it does not look nice with the duplication. However, the existing implementation is easy to follow,
> and I could not figure out a way that can easily generalize over vgpr class without make the code messy.
>
> We will continue to work on to come out with a generalized solution. But in the mean time, we need 
> the fix for a correctness issue which has been bothering us for a long time.

GlobalISel already has a generalized implementation, it just relies on generic registers. I'd rather copy something from there and dirty it up with register classes



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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4986
+  else // Not implemented yet.
+    assert(false && "waterfall loop not imlemented for Rsrc size");
 
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llvm_unreachable


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