[PATCH] D81766: [VectorCombine] try to create vector loads from scalar loads

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D81766#2211991 <https://reviews.llvm.org/D81766#2211991>, @spatel wrote:

> In D81766#2211952 <https://reviews.llvm.org/D81766#2211952>, @srj wrote:
>
>>> Can we just add another condition (!VectorSize) to this bailout?
>>> if (!ScalarSize || VectorSize % ScalarSize != 0)
>>
>> Changing it to `if (!ScalarSize || !VectorSize || VectorSize % ScalarSize != 0)` does indeed seem to make our failure go away, so that would be fine as a quick fix.
>>
>> (I'm still surprised that `getMinVectorRegisterBitWidth()` should ever return 0, but I can take that up with Qualcomm folks separately; it is entirely possible I don't understand the full semantics of that method.)
>
> rGb0b95dab1ce2 <https://reviews.llvm.org/rGb0b95dab1ce21d93f3d62bc37256da9f38cff616> 
> l'll see if I can find a better API and/or test case for that tomorrow.

Test added here:
rGb97e402ca5ba <https://reviews.llvm.org/rGb97e402ca5ba3d1a4795ed61f8cb36783b00ed44>

The Loop and SLP vectorizers check this:

  // If the target claims to have no vector registers don't attempt
  // vectorization.
  if (!TTI->getNumberOfRegisters(TTI->getRegisterClassForType(true)))
    return false;

So I should probably add that check to this pass too to be safer.


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