[llvm] b0b95da - [VectorCombine] add safety check for 0-width register

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-08-11T20:30:02-04:00
New Revision: b0b95dab1ce21d93f3d62bc37256da9f38cff616

URL: https://github.com/llvm/llvm-project/commit/b0b95dab1ce21d93f3d62bc37256da9f38cff616
DIFF: https://github.com/llvm/llvm-project/commit/b0b95dab1ce21d93f3d62bc37256da9f38cff616.diff

LOG: [VectorCombine] add safety check for 0-width register

Based on post-commit discussion in D81766, Hexagon sets this to "0".
I'll see if I can come up with a test, but making the obvious
code fix first to unblock that target.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/VectorCombine.cpp

Removed: 
    


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diff  --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 688ea8fa2343..7faba73abf0f 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -107,7 +107,7 @@ bool VectorCombine::vectorizeLoadInsert(Instruction &I) {
 
   unsigned VectorSize = TTI.getMinVectorRegisterBitWidth();
   uint64_t ScalarSize = ScalarTy->getPrimitiveSizeInBits();
-  if (!ScalarSize || VectorSize % ScalarSize != 0)
+  if (!ScalarSize || !VectorSize || VectorSize % ScalarSize != 0)
     return false;
 
   // Check safety of replacing the scalar load with a larger vector load.