[PATCH] D85757: [DebugInstrRef][6/9] Pass DBG_INSTR_REFs safely through register allocation

[Jeremy Morse via Phabricator via llvm-commits]

jmorse created this revision.
jmorse added a reviewer: debug-info.
Herald added subscribers: llvm-commits, hiraditya, MatzeB.
Herald added a project: LLVM.
jmorse requested review of this revision.

Both FastRegAlloc and LiveDebugVariables/greedy need to cope with DBG_INSTR_REFs. None of them actually need to take any action, other than passing DBG_INSTR_REFs through: variable location information doesn't refer to any registers at this stage.

LiveDebugVariables stashes the instruction information in a tuple, then re-creates it later. This is only necessary as the register allocator doesn't expect to see any debug instructions while it's working. No equivalence classes or interval splitting is required at all!

No changes are needed for the fast register allocator, as it just ignores debug instructions. The test added checks that both of them preserve DBG_INSTR_REFs.

I also expand ScheduleDAGInstrs.cpp to treat DBG_INSTR_REFs as DBG_VALUEs when rescheduling instructions around -- done in this patch as machine-scheduler is part of the register allocation phase, as I understand it. The current movement of DBG_VALUEs around is less than ideal, but it's not a regression to make DBG_INSTR_REFs subject to the same movement.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85757

Files:
  llvm/lib/CodeGen/LiveDebugVariables.cpp
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D85757.284809.patch
Type: text/x-patch
Size: 9466 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200811/7344d950/attachment.bin>