[PATCH] D85233: [GlobalISel] Implement bit-test switch table optimization

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll:132
+  ret void
+}
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Can you add a few degenerate cases with 1 and 2 switch cases (and 0 if that's even accepted).

I also don't think any of these hit the omit-branch-to-next block case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85233/new/

https://reviews.llvm.org/D85233