[PATCH] D85653: [GlobalISel][AMDGPU] Lower G_SMULH/G_UMULH

[Jay Foad via Phabricator via llvm-commits]

foad requested changes to this revision.
foad added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:6010
+  bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH;
+  unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
+  Register Result = MI.getOperand(0).getReg();
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I agree that anyext would not work here.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:6013
+  auto SizeInBits = MRI.getType(Result).getScalarSizeInBits();
+  LLT WideTy = LLT::scalar(SizeInBits * 2);
+
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Would this lowering also work for vector types, if you used LLT::scalarOrVector here?


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:6020
+
+  auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits - IsSigned);
+  auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt});
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As Matt said you definitely should not subtract IsSigned here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85653/new/

https://reviews.llvm.org/D85653