[PATCH] D85546: [SVE] Add ISD nodes for predicated integer extend inreg operations

[Paul Walker via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb6c7b7fa31b7: [SVE] Add ISD nodes for predicated integer extend inreg operations. (authored by paulwalker-arm).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85546/new/

https://reviews.llvm.org/D85546

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D85546.284638.patch
Type: text/x-patch
Size: 8487 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200811/86db6475/attachment.bin>