[PATCH] D85720: [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()

[Raul Tambre via Phabricator via llvm-commits]

tambre created this revision.
tambre added a reviewer: paquette.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls, rovka.
Herald added a project: LLVM.
tambre requested review of this revision.

TargetRegisterInfo::getMinimalPhysRegClass() returns rtcGPR64RegClassID for X16 and X17, as it's the last matching class.
This in turn gets passed to AArch64RegisterBankInfo::getRegBankFromRegClass(), which hits an unreachable.

It seems sensible to handle this case, so copies from X16 and X17 work.
Copying from X17 is used in inline assembly in libunwind for pointer authentication.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85720

Files:
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -75,6 +75,8 @@
 
   define void @test_gphi_ptr() { ret void }
 
+  define void @test_restricted_tail_call() { ret void }
+
 ...
 
 ---
@@ -888,3 +890,15 @@
     RET_ReallyLR implicit $x0
 
 ...
+
+---
+name:            test_restricted_tail_call
+legalized:       true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x16, $x17
+    %0:_(s64) = COPY $x16
+    %1:_(s64) = COPY $x17
+    RET_ReallyLR
+...
Index: llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -261,6 +261,7 @@
   case AArch64::GPR64common_and_GPR64noipRegClassID:
   case AArch64::GPR64noip_and_tcGPR64RegClassID:
   case AArch64::tcGPR64RegClassID:
+  case AArch64::rtcGPR64RegClassID:
   case AArch64::WSeqPairsClassRegClassID:
   case AArch64::XSeqPairsClassRegClassID:
     return getRegBank(AArch64::GPRRegBankID);


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