[PATCH] D85640: [SVE] Lower fixed length integer extend operations.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll:98
+define void @sext_v16i8_v16i32(<16 x i8> %a, <16 x i32>* %out) #0 {
+; CHECK-LABEL: sext_v16i8_v16i32:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
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Maybe worth adding a couple CHECK lines for sext_v16i8_v16i32 if the fixed vector width is 256, to make sure we do something sane if we need to legalize the result type?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85640/new/

https://reviews.llvm.org/D85640