[llvm] 81883ca - [PowerPC] Add option to control PCRel GOT indirect linker optimization

Stefan Pintilie via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 10 07:07:28 PDT 2020


Author: Stefan Pintilie
Date: 2020-08-10T09:07:17-05:00
New Revision: 81883ca074556f9598a8a2f43ccfb81489baeb78

URL: https://github.com/llvm/llvm-project/commit/81883ca074556f9598a8a2f43ccfb81489baeb78
DIFF: https://github.com/llvm/llvm-project/commit/81883ca074556f9598a8a2f43ccfb81489baeb78.diff

LOG: [PowerPC] Add option to control PCRel GOT indirect linker optimization

Add a hidden option to the compiler to control a the PC Relative GOT indirect
linker optimization.

If this option is set to false the compiler will no loger produce the
relocations required by the linker to perform the optimization.

Reviewed By: nemanjai, NeHuang, #powerpc

Differential Revision: https://reviews.llvm.org/D85377

Added: 
    llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index 65539166e5ef..7d1282df369b 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -38,6 +38,10 @@ STATISTIC(NumberOfSelfCopies,
 STATISTIC(NumFrameOffFoldInPreEmit,
           "Number of folding frame offset by using r+r in pre-emit peephole");
 
+static cl::opt<bool>
+EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true),
+                     cl::desc("enable PC Relative linker optimization"));
+
 static cl::opt<bool>
 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
                    cl::desc("Run pre-emit peephole optimizations."));
@@ -234,6 +238,10 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
 
     bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
       MachineFunction *MF = MBB.getParent();
+      // If the linker opt is disabled then just return.
+      if (!EnablePCRelLinkerOpt)
+        return false;
+
       // Add this linker opt only if we are using PC Relative memops.
       if (!MF->getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls())
         return false;

diff  --git a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll
new file mode 100644
index 000000000000..8e470b6f8ccb
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s | FileCheck %s --check-prefix=DEFAULT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-pcrel-linker-opt=true < %s | FileCheck %s --check-prefix=ON
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -ppc-pcrel-linker-opt=false < %s | FileCheck %s --check-prefix=OFF
+
+ at input8 = external local_unnamed_addr global i8, align 1
+
+define dso_local i8 @Read8() local_unnamed_addr {
+; DEFAULT-LABEL: Read8:
+; DEFAULT:       # %bb.0: # %entry
+; DEFAULT-NEXT:    pld r3, input8 at got@pcrel(0), 1
+; DEFAULT-NEXT:  .Lpcrel:
+; DEFAULT-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; DEFAULT-NEXT:    lbz r3, 0(r3)
+; DEFAULT-NEXT:    blr
+;
+; ON-LABEL: Read8:
+; ON:       # %bb.0: # %entry
+; ON-NEXT:    pld r3, input8 at got@pcrel(0), 1
+; ON-NEXT:  .Lpcrel:
+; ON-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; ON-NEXT:    lbz r3, 0(r3)
+; ON-NEXT:    blr
+;
+; OFF-LABEL: Read8:
+; OFF:       # %bb.0: # %entry
+; OFF-NEXT:    pld r3, input8 at got@pcrel(0), 1
+; OFF-NEXT:    lbz r3, 0(r3)
+; OFF-NEXT:    blr
+entry:
+  %0 = load i8, i8* @input8, align 1
+  ret i8 %0
+}


        


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