[llvm] 40188f8 - AMDGPU/GlobalISel: Don't try to handle undef source operand

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-10T08:49:43-04:00
New Revision: 40188f807dc7e59a5d1db9cd5d59f234af2aa2d6

URL: https://github.com/llvm/llvm-project/commit/40188f807dc7e59a5d1db9cd5d59f234af2aa2d6
DIFF: https://github.com/llvm/llvm-project/commit/40188f807dc7e59a5d1db9cd5d59f234af2aa2d6.diff

LOG: AMDGPU/GlobalISel: Don't try to handle undef source operand

This is now illegal MIR

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index dc9af074d315..ffc7e1a4a8bd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -557,8 +557,6 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
   if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
     return false;
 
-  const unsigned SrcFlags = getUndefRegState(Src.isUndef());
-
   // Note we could have mixed SGPR and VGPR destination banks for an SGPR
   // source, and this relies on the fact that the same subregister indices are
   // used for both.
@@ -566,7 +564,7 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
   for (int I = 0, E = NumDst; I != E; ++I) {
     MachineOperand &Dst = MI.getOperand(I);
     BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
-      .addReg(SrcReg, SrcFlags, SubRegs[I]);
+      .addReg(SrcReg, 0, SubRegs[I]);
 
     // Make sure the subregister index is valid for the source register.
     SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);