[llvm] 1675f8a - [TableGen] Pull the increment of a variable out of an assert.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-08-09T20:24:56-07:00
New Revision: 1675f8a2516d0a6f90744aef1066482ee072bbc8

URL: https://github.com/llvm/llvm-project/commit/1675f8a2516d0a6f90744aef1066482ee072bbc8
DIFF: https://github.com/llvm/llvm-project/commit/1675f8a2516d0a6f90744aef1066482ee072bbc8.diff

LOG: [TableGen] Pull the increment of a variable out of an assert.

The variable is only used by the assert so the code was fine
before, but it was flagged in PR47072.

Added: 
    

Modified: 
    llvm/utils/TableGen/RegisterInfoEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index a615587efdee..b30a8b3fa6c2 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1288,7 +1288,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
         OS << CGH.getMode(M).Name;
       OS << ")\n";
       for (const auto &RC : RegisterClasses) {
-        assert(RC.EnumValue == EV++ && "Unexpected order of register classes");
+        assert(RC.EnumValue == EV && "Unexpected order of register classes");
+        ++EV;
         (void)EV;
         const RegSizeInfo &RI = RC.RSI.get(M);
         OS << "  { " << RI.RegSize << ", " << RI.SpillSize << ", "