[llvm] bc8be30 - [X86][GlobalISel] Remove unneeded code for handling zext i8->16, i8->i64, i16->i64, i32->i64.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 9 00:27:01 PDT 2020
Author: Craig Topper
Date: 2020-08-09T00:26:15-07:00
New Revision: bc8be3054067ac822fc6d9f4f8e64c841f530f16
URL: https://github.com/llvm/llvm-project/commit/bc8be3054067ac822fc6d9f4f8e64c841f530f16
DIFF: https://github.com/llvm/llvm-project/commit/bc8be3054067ac822fc6d9f4f8e64c841f530f16.diff
LOG: [X86][GlobalISel] Remove unneeded code for handling zext i8->16, i8->i64, i16->i64, i32->i64.
These all seem to be handled by tablegen pattern imports.
Added:
Modified:
llvm/lib/Target/X86/X86InstructionSelector.cpp
llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
llvm/test/CodeGen/X86/GlobalISel/ext.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index 60fb4d2ef4bf..4b8ca29b9f38 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -780,69 +780,18 @@ bool X86InstructionSelector::selectZext(MachineInstr &I,
const LLT DstTy = MRI.getType(DstReg);
const LLT SrcTy = MRI.getType(SrcReg);
+ assert(!(SrcTy == LLT::scalar(8) && DstTy == LLT::scalar(16)) &&
+ "8=>16 Zext is handled by tablegen");
assert(!(SrcTy == LLT::scalar(8) && DstTy == LLT::scalar(32)) &&
"8=>32 Zext is handled by tablegen");
assert(!(SrcTy == LLT::scalar(16) && DstTy == LLT::scalar(32)) &&
"16=>32 Zext is handled by tablegen");
-
- const static struct ZextEntry {
- LLT SrcTy;
- LLT DstTy;
- unsigned MovOp;
- bool NeedSubregToReg;
- } OpTable[] = {
- {LLT::scalar(8), LLT::scalar(16), X86::MOVZX16rr8, false}, // i8 => i16
- {LLT::scalar(8), LLT::scalar(64), X86::MOVZX32rr8, true}, // i8 => i64
- {LLT::scalar(16), LLT::scalar(64), X86::MOVZX32rr16, true}, // i16 => i64
- {LLT::scalar(32), LLT::scalar(64), 0, true} // i32 => i64
- };
-
- auto ZextEntryIt =
- std::find_if(std::begin(OpTable), std::end(OpTable),
- [SrcTy, DstTy](const ZextEntry &El) {
- return El.DstTy == DstTy && El.SrcTy == SrcTy;
- });
-
- // Here we try to select Zext into a MOVZ and/or SUBREG_TO_REG instruction.
- if (ZextEntryIt != std::end(OpTable)) {
- const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
- const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
- const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
- const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
-
- if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
- !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
- LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
- << " operand\n");
- return false;
- }
-
- unsigned TransitRegTo = DstReg;
- unsigned TransitRegFrom = SrcReg;
- if (ZextEntryIt->MovOp) {
- // If we select Zext into MOVZ + SUBREG_TO_REG, we need to have
- // a transit register in between: create it here.
- if (ZextEntryIt->NeedSubregToReg) {
- TransitRegFrom = MRI.createVirtualRegister(
- getRegClass(LLT::scalar(32), DstReg, MRI));
- TransitRegTo = TransitRegFrom;
- }
-
- BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp))
- .addDef(TransitRegTo)
- .addReg(SrcReg);
- }
- if (ZextEntryIt->NeedSubregToReg) {
- BuildMI(*I.getParent(), I, I.getDebugLoc(),
- TII.get(TargetOpcode::SUBREG_TO_REG))
- .addDef(DstReg)
- .addImm(0)
- .addReg(TransitRegFrom)
- .addImm(X86::sub_32bit);
- }
- I.eraseFromParent();
- return true;
- }
+ assert(!(SrcTy == LLT::scalar(8) && DstTy == LLT::scalar(64)) &&
+ "8=>64 Zext is handled by tablegen");
+ assert(!(SrcTy == LLT::scalar(16) && DstTy == LLT::scalar(64)) &&
+ "16=>64 Zext is handled by tablegen");
+ assert(!(SrcTy == LLT::scalar(32) && DstTy == LLT::scalar(64)) &&
+ "32=>64 Zext is handled by tablegen");
if (SrcTy != LLT::scalar(1))
return false;
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll b/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
index ce9637b4b1e3..26ee839b614e 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
@@ -42,3 +42,35 @@ define i64 @test_sext_i16(i16 %val) {
; ret i64 %r
;}
+define i64 @test_zext_i8_to_i64(i8 %x, i8 %y) {
+; X64-LABEL: test_zext_i8_to_i64:
+; X64: # %bb.0:
+; X64-NEXT: addb %dil, %sil
+; X64-NEXT: movzbl %sil, %eax
+; X64-NEXT: retq
+ %a = add i8 %x, %y
+ %b = zext i8 %a to i64
+ ret i64 %b
+}
+
+define i64 @test_zext_i16_to_i64(i16 %x, i16 %y) {
+; X64-LABEL: test_zext_i16_to_i64:
+; X64: # %bb.0:
+; X64-NEXT: addw %di, %si
+; X64-NEXT: movzwl %si, %eax
+; X64-NEXT: retq
+ %a = add i16 %x, %y
+ %b = zext i16 %a to i64
+ ret i64 %b
+}
+
+define i64 @test_zext_i32_to_i64(i32 %x, i32 %y) {
+; X64-LABEL: test_zext_i32_to_i64:
+; X64: # %bb.0:
+; X64-NEXT: addl %edi, %esi
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: retq
+ %a = add i32 %x, %y
+ %b = zext i32 %a to i64
+ ret i64 %b
+}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ext.ll b/llvm/test/CodeGen/X86/GlobalISel/ext.ll
index 953f3ff953db..cdd7694f30fc 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/ext.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ext.ll
@@ -117,3 +117,22 @@ define i32 @test_sext_i16(i16 %val) {
ret i32 %r
}
+define i16 @test_zext_i8_to_i16(i8 %x, i8 %y) {
+; X64-LABEL: test_zext_i8_to_i16:
+; X64: # %bb.0:
+; X64-NEXT: addb %dil, %sil
+; X64-NEXT: movzbl %sil, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+;
+; X32-LABEL: test_zext_i8_to_i16:
+; X32: # %bb.0:
+; X32-NEXT: movb {{[0-9]+}}(%esp), %al
+; X32-NEXT: addb {{[0-9]+}}(%esp), %al
+; X32-NEXT: movzbl %al, %eax
+; X32-NEXT: # kill: def $ax killed $ax killed $eax
+; X32-NEXT: retl
+ %a = add i8 %x, %y
+ %b = zext i8 %a to i16
+ ret i16 %b
+}
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