[llvm] 44b260c - [X86] Increase the number of instructions searched for isSafeToClobberEFLAGS in a couple places
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 8 11:38:01 PDT 2020
I mixed up bug numbers that should have been PR46315 instead of PR43014
~Craig
On Sat, Aug 8, 2020 at 11:33 AM Craig Topper via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
>
> Author: Craig Topper
> Date: 2020-08-08T11:29:41-07:00
> New Revision: 44b260cb0aab387d85e4d59c16fc7b8866264f5e
>
> URL:
> https://github.com/llvm/llvm-project/commit/44b260cb0aab387d85e4d59c16fc7b8866264f5e
> DIFF:
> https://github.com/llvm/llvm-project/commit/44b260cb0aab387d85e4d59c16fc7b8866264f5e.diff
>
> LOG: [X86] Increase the number of instructions searched for
> isSafeToClobberEFLAGS in a couple places
>
> Previously this function searched 4 instructions forwards or
> backwards to determine if it was ok to clobber eflags.
>
> This is called in 3 places: rematerialization, turning 2 operand
> leas into adds or splitting 3 ops leas into an lea and add on some
> CPU targets.
>
> This patch increases the search limit to 10 instructions for
> rematerialization and 2 operand lea to add. I've left the old
> treshold for 3 ops lea spliting as that increases code size.
>
> Fixes PR47024 and PR43014
>
> Added:
>
>
> Modified:
> llvm/lib/Target/X86/X86FixupLEAs.cpp
> llvm/lib/Target/X86/X86InstrInfo.cpp
> llvm/lib/Target/X86/X86InstrInfo.h
> llvm/test/CodeGen/X86/optimize-max-0.ll
>
> Removed:
>
>
>
>
> ################################################################################
> diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp
> b/llvm/lib/Target/X86/X86FixupLEAs.cpp
> index 424279038921..fcc3e8f781a3 100644
> --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
> +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
> @@ -376,7 +376,7 @@ bool
> FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
> const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
>
> if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
> - !TII->isSafeToClobberEFLAGS(MBB, I))
> + !TII->isSafeToClobberEFLAGS(MBB, I, 10))
> return false;
>
> Register DestReg = MI.getOperand(0).getReg();
>
> diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp
> b/llvm/lib/Target/X86/X86InstrInfo.cpp
> index c753880fc92c..b27959ad9bf5 100644
> --- a/llvm/lib/Target/X86/X86InstrInfo.cpp
> +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
> @@ -1127,7 +1127,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock
> &MBB,
> const MachineInstr &Orig,
> const TargetRegisterInfo &TRI) const {
> bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
> - if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
> + if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I, 10)) {
> // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to
> avoid side
> // effects.
> int Value;
>
> diff --git a/llvm/lib/Target/X86/X86InstrInfo.h
> b/llvm/lib/Target/X86/X86InstrInfo.h
> index c345a8217168..60b7d51bf9e4 100644
> --- a/llvm/lib/Target/X86/X86InstrInfo.h
> +++ b/llvm/lib/Target/X86/X86InstrInfo.h
> @@ -442,8 +442,9 @@ class X86InstrInfo final : public X86GenInstrInfo {
> /// conservative. If it cannot definitely determine the safety after
> visiting
> /// a few instructions in each direction it assumes it's not safe.
> bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
> - MachineBasicBlock::iterator I) const {
> - return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, 4) ==
> + MachineBasicBlock::iterator I,
> + unsigned Neighborhood = 4) const {
> + return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, Neighborhood)
> ==
> MachineBasicBlock::LQR_Dead;
> }
>
>
> diff --git a/llvm/test/CodeGen/X86/optimize-max-0.ll
> b/llvm/test/CodeGen/X86/optimize-max-0.ll
> index e7f885625b76..5367f390d1cb 100644
> --- a/llvm/test/CodeGen/X86/optimize-max-0.ll
> +++ b/llvm/test/CodeGen/X86/optimize-max-0.ll
> @@ -85,7 +85,7 @@ define void @foo(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j,
> i32 %d) nounwind {
> ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
> ; CHECK-NEXT: addl %ecx, %eax
> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
> -; CHECK-NEXT: leal 2(%esi), %esi
> +; CHECK-NEXT: addl $2, %esi
> ; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
> ; CHECK-NEXT: movl (%esp), %esi ## 4-byte Reload
> ; CHECK-NEXT: addl %esi, %ecx
> @@ -513,7 +513,7 @@ define void @bar(i8* %r, i32 %s, i32 %w, i32 %x, i8*
> %j, i32 %d) nounwind {
> ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
> ; CHECK-NEXT: addl %eax, %ecx
> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
> -; CHECK-NEXT: leal 2(%edx), %edx
> +; CHECK-NEXT: addl $2, %edx
> ; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
> ; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Reload
> ; CHECK-NEXT: addl %edx, %eax
>
>
>
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