[llvm] 514b00c - [X86] Limit the scope of the min/max canonicalization in combineSelect
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 22:52:04 PDT 2020
Author: Craig Topper
Date: 2020-08-07T22:51:49-07:00
New Revision: 514b00c43996221b90ce581bfb18b6af7caed5f6
URL: https://github.com/llvm/llvm-project/commit/514b00c43996221b90ce581bfb18b6af7caed5f6
DIFF: https://github.com/llvm/llvm-project/commit/514b00c43996221b90ce581bfb18b6af7caed5f6.diff
LOG: [X86] Limit the scope of the min/max canonicalization in combineSelect
Previously the transform was doing these two canonicalizations
(x > y) ? x : y -> (x >= y) ? x : y
(x < y) ? x : y -> (x <= y) ? x : y
But those don't seem to be useful generally. And they actively
pessimize the cases in PR47049.
This patch limits it to
(x > 0) ? x : 0 -> (x >= 0) ? x : 0
(x < -1) ? x : -1 -> (x <= -1) ? x : -1
These are the cases mentioned in the comments as the motivation
for the canonicalization. These allow the CMOV to use the S
flag from the compare thus improving opportunities to use a TEST
or the flags from an arithmetic instruction.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
llvm/test/CodeGen/X86/atomic128.ll
llvm/test/CodeGen/X86/atomic32.ll
llvm/test/CodeGen/X86/atomic64.ll
llvm/test/CodeGen/X86/atomic6432.ll
llvm/test/CodeGen/X86/cmov.ll
llvm/test/CodeGen/X86/pr5145.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 37a8b4a998cb..b8e7026d1ca4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -40163,13 +40163,13 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
if (SDValue V = combineSelectOfTwoConstants(N, DAG))
return V;
- // Canonicalize max and min:
- // (x > y) ? x : y -> (x >= y) ? x : y
- // (x < y) ? x : y -> (x <= y) ? x : y
+ // Canonicalize min/max:
+ // (x > 0) ? x : 0 -> (x >= 0) ? x : 0
+ // (x < -1) ? x : -1 -> (x <= -1) ? x : -1
// This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
// the need for an extra compare
// against zero. e.g.
- // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
+ // (a - b) > 0 : (a - b) ? 0 -> (a - b) >= 0 : (a - b) ? 0
// subl %esi, %edi
// testl %edi, %edi
// movl $0, %eax
@@ -40180,19 +40180,15 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// cmovsl %eax, %edi
if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
Cond.hasOneUse() &&
- DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
- DAG.isEqualTo(RHS, Cond.getOperand(1))) {
+ LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
- switch (CC) {
- default: break;
- case ISD::SETLT:
- case ISD::SETGT: {
- ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
+ if ((CC == ISD::SETGT && isNullConstant(RHS)) ||
+ (CC == ISD::SETLT && isAllOnesConstant(RHS))) {
+ ISD::CondCode NewCC = CC == ISD::SETGT ? ISD::SETGE : ISD::SETLE;
Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
Cond.getOperand(0), Cond.getOperand(1), NewCC);
return DAG.getSelect(DL, VT, Cond, LHS, RHS);
}
- }
}
// Match VSELECTs into subs with unsigned saturation.
diff --git a/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll b/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
index c8235e8d0965..2cfc6e1163c9 100644
--- a/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
+++ b/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
@@ -16,7 +16,7 @@ define i8 @t0(i32 %a1_wide_orig, i32 %a2_wide_orig, i32 %inc) nounwind {
; I386-NOCMOV-NEXT: addl %ecx, %eax
; I386-NOCMOV-NEXT: addl {{[0-9]+}}(%esp), %ecx
; I386-NOCMOV-NEXT: cmpb %cl, %al
-; I386-NOCMOV-NEXT: jge .LBB0_2
+; I386-NOCMOV-NEXT: jg .LBB0_2
; I386-NOCMOV-NEXT: # %bb.1:
; I386-NOCMOV-NEXT: movl %ecx, %eax
; I386-NOCMOV-NEXT: .LBB0_2:
@@ -30,7 +30,7 @@ define i8 @t0(i32 %a1_wide_orig, i32 %a2_wide_orig, i32 %inc) nounwind {
; I386-CMOV-NEXT: addl %eax, %ecx
; I386-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax
; I386-CMOV-NEXT: cmpb %al, %cl
-; I386-CMOV-NEXT: cmovgel %ecx, %eax
+; I386-CMOV-NEXT: cmovgl %ecx, %eax
; I386-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I386-CMOV-NEXT: retl
;
@@ -41,7 +41,7 @@ define i8 @t0(i32 %a1_wide_orig, i32 %a2_wide_orig, i32 %inc) nounwind {
; I686-NOCMOV-NEXT: addl %ecx, %eax
; I686-NOCMOV-NEXT: addl {{[0-9]+}}(%esp), %ecx
; I686-NOCMOV-NEXT: cmpb %cl, %al
-; I686-NOCMOV-NEXT: jge .LBB0_2
+; I686-NOCMOV-NEXT: jg .LBB0_2
; I686-NOCMOV-NEXT: # %bb.1:
; I686-NOCMOV-NEXT: movl %ecx, %eax
; I686-NOCMOV-NEXT: .LBB0_2:
@@ -55,7 +55,7 @@ define i8 @t0(i32 %a1_wide_orig, i32 %a2_wide_orig, i32 %inc) nounwind {
; I686-CMOV-NEXT: addl %eax, %ecx
; I686-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax
; I686-CMOV-NEXT: cmpb %al, %cl
-; I686-CMOV-NEXT: cmovgel %ecx, %eax
+; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl
;
@@ -65,7 +65,7 @@ define i8 @t0(i32 %a1_wide_orig, i32 %a2_wide_orig, i32 %inc) nounwind {
; X86_64-NEXT: addl %edx, %edi
; X86_64-NEXT: addl %edx, %eax
; X86_64-NEXT: cmpb %al, %dil
-; X86_64-NEXT: cmovgel %edi, %eax
+; X86_64-NEXT: cmovgl %edi, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq
%a1_wide = add i32 %a1_wide_orig, %inc
@@ -87,7 +87,7 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
; I386-NOCMOV-NEXT: addl %ecx, %eax
; I386-NOCMOV-NEXT: addb {{[0-9]+}}(%esp), %cl
; I386-NOCMOV-NEXT: cmpb %cl, %al
-; I386-NOCMOV-NEXT: jge .LBB1_2
+; I386-NOCMOV-NEXT: jg .LBB1_2
; I386-NOCMOV-NEXT: # %bb.1:
; I386-NOCMOV-NEXT: movl %ecx, %eax
; I386-NOCMOV-NEXT: .LBB1_2:
@@ -102,7 +102,7 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
; I386-CMOV-NEXT: addb {{[0-9]+}}(%esp), %al
; I386-CMOV-NEXT: cmpb %al, %cl
; I386-CMOV-NEXT: movzbl %al, %eax
-; I386-CMOV-NEXT: cmovgel %ecx, %eax
+; I386-CMOV-NEXT: cmovgl %ecx, %eax
; I386-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I386-CMOV-NEXT: retl
;
@@ -113,7 +113,7 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
; I686-NOCMOV-NEXT: addl %ecx, %eax
; I686-NOCMOV-NEXT: addb {{[0-9]+}}(%esp), %cl
; I686-NOCMOV-NEXT: cmpb %cl, %al
-; I686-NOCMOV-NEXT: jge .LBB1_2
+; I686-NOCMOV-NEXT: jg .LBB1_2
; I686-NOCMOV-NEXT: # %bb.1:
; I686-NOCMOV-NEXT: movl %ecx, %eax
; I686-NOCMOV-NEXT: .LBB1_2:
@@ -128,7 +128,7 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
; I686-CMOV-NEXT: addb {{[0-9]+}}(%esp), %al
; I686-CMOV-NEXT: cmpb %al, %cl
; I686-CMOV-NEXT: movzbl %al, %eax
-; I686-CMOV-NEXT: cmovgel %ecx, %eax
+; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl
;
@@ -138,7 +138,7 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
; X86_64-NEXT: addb %sil, %dl
; X86_64-NEXT: cmpb %dl, %dil
; X86_64-NEXT: movzbl %dl, %eax
-; X86_64-NEXT: cmovgel %edi, %eax
+; X86_64-NEXT: cmovgl %edi, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq
%a1_wide = add i32 %a1_wide_orig, %inc
@@ -160,7 +160,7 @@ define i8 @neg_type_mismatch(i32 %a1_wide_orig, i16 %a2_wide_orig, i32 %inc) nou
; I386-NOCMOV-NEXT: addl %ecx, %eax
; I386-NOCMOV-NEXT: addw {{[0-9]+}}(%esp), %cx
; I386-NOCMOV-NEXT: cmpb %cl, %al
-; I386-NOCMOV-NEXT: jge .LBB2_2
+; I386-NOCMOV-NEXT: jg .LBB2_2
; I386-NOCMOV-NEXT: # %bb.1:
; I386-NOCMOV-NEXT: movl %ecx, %eax
; I386-NOCMOV-NEXT: .LBB2_2:
@@ -174,7 +174,7 @@ define i8 @neg_type_mismatch(i32 %a1_wide_orig, i16 %a2_wide_orig, i32 %inc) nou
; I386-CMOV-NEXT: addl %eax, %ecx
; I386-CMOV-NEXT: addw {{[0-9]+}}(%esp), %ax
; I386-CMOV-NEXT: cmpb %al, %cl
-; I386-CMOV-NEXT: cmovgel %ecx, %eax
+; I386-CMOV-NEXT: cmovgl %ecx, %eax
; I386-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I386-CMOV-NEXT: retl
;
@@ -185,7 +185,7 @@ define i8 @neg_type_mismatch(i32 %a1_wide_orig, i16 %a2_wide_orig, i32 %inc) nou
; I686-NOCMOV-NEXT: addl %ecx, %eax
; I686-NOCMOV-NEXT: addw {{[0-9]+}}(%esp), %cx
; I686-NOCMOV-NEXT: cmpb %cl, %al
-; I686-NOCMOV-NEXT: jge .LBB2_2
+; I686-NOCMOV-NEXT: jg .LBB2_2
; I686-NOCMOV-NEXT: # %bb.1:
; I686-NOCMOV-NEXT: movl %ecx, %eax
; I686-NOCMOV-NEXT: .LBB2_2:
@@ -199,7 +199,7 @@ define i8 @neg_type_mismatch(i32 %a1_wide_orig, i16 %a2_wide_orig, i32 %inc) nou
; I686-CMOV-NEXT: addl %eax, %ecx
; I686-CMOV-NEXT: addw {{[0-9]+}}(%esp), %ax
; I686-CMOV-NEXT: cmpb %al, %cl
-; I686-CMOV-NEXT: cmovgel %ecx, %eax
+; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl
;
@@ -209,7 +209,7 @@ define i8 @neg_type_mismatch(i32 %a1_wide_orig, i16 %a2_wide_orig, i32 %inc) nou
; X86_64-NEXT: addl %edx, %edi
; X86_64-NEXT: addl %edx, %eax
; X86_64-NEXT: cmpb %al, %dil
-; X86_64-NEXT: cmovgel %edi, %eax
+; X86_64-NEXT: cmovgl %edi, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq
%a1_wide = add i32 %a1_wide_orig, %inc
@@ -231,7 +231,7 @@ define i8 @negative_CopyFromReg(i32 %a1_wide, i32 %a2_wide_orig, i32 %inc) nounw
; I386-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I386-NOCMOV-NEXT: addl {{[0-9]+}}(%esp), %ecx
; I386-NOCMOV-NEXT: cmpb %cl, %al
-; I386-NOCMOV-NEXT: jge .LBB3_2
+; I386-NOCMOV-NEXT: jg .LBB3_2
; I386-NOCMOV-NEXT: # %bb.1:
; I386-NOCMOV-NEXT: movl %ecx, %eax
; I386-NOCMOV-NEXT: .LBB3_2:
@@ -243,7 +243,7 @@ define i8 @negative_CopyFromReg(i32 %a1_wide, i32 %a2_wide_orig, i32 %inc) nounw
; I386-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; I386-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax
; I386-CMOV-NEXT: cmpb %al, %cl
-; I386-CMOV-NEXT: cmovgel %ecx, %eax
+; I386-CMOV-NEXT: cmovgl %ecx, %eax
; I386-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I386-CMOV-NEXT: retl
;
@@ -253,7 +253,7 @@ define i8 @negative_CopyFromReg(i32 %a1_wide, i32 %a2_wide_orig, i32 %inc) nounw
; I686-NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I686-NOCMOV-NEXT: addl {{[0-9]+}}(%esp), %ecx
; I686-NOCMOV-NEXT: cmpb %cl, %al
-; I686-NOCMOV-NEXT: jge .LBB3_2
+; I686-NOCMOV-NEXT: jg .LBB3_2
; I686-NOCMOV-NEXT: # %bb.1:
; I686-NOCMOV-NEXT: movl %ecx, %eax
; I686-NOCMOV-NEXT: .LBB3_2:
@@ -265,7 +265,7 @@ define i8 @negative_CopyFromReg(i32 %a1_wide, i32 %a2_wide_orig, i32 %inc) nounw
; I686-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; I686-CMOV-NEXT: addl {{[0-9]+}}(%esp), %eax
; I686-CMOV-NEXT: cmpb %al, %cl
-; I686-CMOV-NEXT: cmovgel %ecx, %eax
+; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl
;
@@ -274,7 +274,7 @@ define i8 @negative_CopyFromReg(i32 %a1_wide, i32 %a2_wide_orig, i32 %inc) nounw
; X86_64-NEXT: movl %esi, %eax
; X86_64-NEXT: addl %edx, %eax
; X86_64-NEXT: cmpb %al, %dil
-; X86_64-NEXT: cmovgel %edi, %eax
+; X86_64-NEXT: cmovgl %edi, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq
%a2_wide = add i32 %a2_wide_orig, %inc
@@ -293,7 +293,7 @@ define i8 @negative_CopyFromRegs(i32 %a1_wide, i32 %a2_wide) nounwind {
; I386-NOCMOV-NEXT: movb {{[0-9]+}}(%esp), %cl
; I386-NOCMOV-NEXT: movb {{[0-9]+}}(%esp), %al
; I386-NOCMOV-NEXT: cmpb %cl, %al
-; I386-NOCMOV-NEXT: jge .LBB4_2
+; I386-NOCMOV-NEXT: jg .LBB4_2
; I386-NOCMOV-NEXT: # %bb.1:
; I386-NOCMOV-NEXT: movl %ecx, %eax
; I386-NOCMOV-NEXT: .LBB4_2:
@@ -304,7 +304,7 @@ define i8 @negative_CopyFromRegs(i32 %a1_wide, i32 %a2_wide) nounwind {
; I386-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; I386-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I386-CMOV-NEXT: cmpb %al, %cl
-; I386-CMOV-NEXT: cmovgel %ecx, %eax
+; I386-CMOV-NEXT: cmovgl %ecx, %eax
; I386-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I386-CMOV-NEXT: retl
;
@@ -313,7 +313,7 @@ define i8 @negative_CopyFromRegs(i32 %a1_wide, i32 %a2_wide) nounwind {
; I686-NOCMOV-NEXT: movb {{[0-9]+}}(%esp), %cl
; I686-NOCMOV-NEXT: movb {{[0-9]+}}(%esp), %al
; I686-NOCMOV-NEXT: cmpb %cl, %al
-; I686-NOCMOV-NEXT: jge .LBB4_2
+; I686-NOCMOV-NEXT: jg .LBB4_2
; I686-NOCMOV-NEXT: # %bb.1:
; I686-NOCMOV-NEXT: movl %ecx, %eax
; I686-NOCMOV-NEXT: .LBB4_2:
@@ -324,7 +324,7 @@ define i8 @negative_CopyFromRegs(i32 %a1_wide, i32 %a2_wide) nounwind {
; I686-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; I686-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
; I686-CMOV-NEXT: cmpb %al, %cl
-; I686-CMOV-NEXT: cmovgel %ecx, %eax
+; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl
;
@@ -332,7 +332,7 @@ define i8 @negative_CopyFromRegs(i32 %a1_wide, i32 %a2_wide) nounwind {
; X86_64: # %bb.0:
; X86_64-NEXT: movl %esi, %eax
; X86_64-NEXT: cmpb %al, %dil
-; X86_64-NEXT: cmovgel %edi, %eax
+; X86_64-NEXT: cmovgl %edi, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq
%a1 = trunc i32 %a1_wide to i8
diff --git a/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll b/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
index dc759f7a4178..4eb47c0b82e7 100644
--- a/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
+++ b/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
@@ -11,7 +11,7 @@ define i64 @atomic_max_i64() nounwind {
; LINUX-NEXT: pushl %esi
; LINUX-NEXT: movl sc64+4, %edx
; LINUX-NEXT: movl sc64, %eax
-; LINUX-NEXT: movl $4, %esi
+; LINUX-NEXT: movl $5, %esi
; LINUX-NEXT: .p2align 4, 0x90
; LINUX-NEXT: .LBB0_1: # %atomicrmw.start
; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
@@ -40,7 +40,7 @@ define i64 @atomic_max_i64() nounwind {
; PIC-NEXT: movl L_sc64$non_lazy_ptr-L0$pb(%eax), %esi
; PIC-NEXT: movl (%esi), %eax
; PIC-NEXT: movl 4(%esi), %edx
-; PIC-NEXT: movl $4, %edi
+; PIC-NEXT: movl $5, %edi
; PIC-NEXT: .p2align 4, 0x90
; PIC-NEXT: LBB0_1: ## %atomicrmw.start
; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
diff --git a/llvm/test/CodeGen/X86/atomic128.ll b/llvm/test/CodeGen/X86/atomic128.ll
index af32843fbce0..7151df8a0b96 100644
--- a/llvm/test/CodeGen/X86/atomic128.ll
+++ b/llvm/test/CodeGen/X86/atomic128.ll
@@ -437,13 +437,13 @@ define void @fetch_and_max(i128* %p, i128 %bits) {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq %rsi, %rax
-; CHECK-NEXT: movq %rdx, %rcx
-; CHECK-NEXT: sbbq %r8, %rcx
+; CHECK-NEXT: cmpq %rax, %rsi
; CHECK-NEXT: movq %r8, %rcx
-; CHECK-NEXT: cmovgeq %rdx, %rcx
+; CHECK-NEXT: sbbq %rdx, %rcx
+; CHECK-NEXT: movq %r8, %rcx
+; CHECK-NEXT: cmovlq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
-; CHECK-NEXT: cmovgeq %rax, %rbx
+; CHECK-NEXT: cmovlq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB6_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
diff --git a/llvm/test/CodeGen/X86/atomic32.ll b/llvm/test/CodeGen/X86/atomic32.ll
index 3fe5ef8311ce..05a10966a4f1 100644
--- a/llvm/test/CodeGen/X86/atomic32.ll
+++ b/llvm/test/CodeGen/X86/atomic32.ll
@@ -281,7 +281,7 @@ define void @atomic_fetch_max32(i32 %x) nounwind {
; X64-NEXT: movl %eax, %ecx
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %edx # 4-byte Reload
; X64-NEXT: subl %edx, %ecx
-; X64-NEXT: cmovgel %eax, %edx
+; X64-NEXT: cmovgl %eax, %edx
; X64-NEXT: lock cmpxchgl %edx, {{.*}}(%rip)
; X64-NEXT: sete %dl
; X64-NEXT: testb $1, %dl
@@ -305,7 +305,7 @@ define void @atomic_fetch_max32(i32 %x) nounwind {
; X86-CMOV-NEXT: movl %eax, %ecx
; X86-CMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-CMOV-NEXT: subl %edx, %ecx
-; X86-CMOV-NEXT: cmovgel %eax, %edx
+; X86-CMOV-NEXT: cmovgl %eax, %edx
; X86-CMOV-NEXT: lock cmpxchgl %edx, sc32
; X86-CMOV-NEXT: sete %dl
; X86-CMOV-NEXT: testb $1, %dl
@@ -334,7 +334,7 @@ define void @atomic_fetch_max32(i32 %x) nounwind {
; X86-NOCMOV-NEXT: movl %eax, %esi
; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NOCMOV-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NOCMOV-NEXT: jge .LBB6_4
+; X86-NOCMOV-NEXT: jg .LBB6_4
; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start
; X86-NOCMOV-NEXT: # in Loop: Header=BB6_1 Depth=1
; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -374,7 +374,7 @@ define void @atomic_fetch_max32(i32 %x) nounwind {
; X86-NOX87-NEXT: movl %eax, %esi
; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NOX87-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NOX87-NEXT: jge .LBB6_4
+; X86-NOX87-NEXT: jg .LBB6_4
; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start
; X86-NOX87-NEXT: # in Loop: Header=BB6_1 Depth=1
; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
diff --git a/llvm/test/CodeGen/X86/atomic64.ll b/llvm/test/CodeGen/X86/atomic64.ll
index fe7635bdc3ff..963561dc8deb 100644
--- a/llvm/test/CodeGen/X86/atomic64.ll
+++ b/llvm/test/CodeGen/X86/atomic64.ll
@@ -371,7 +371,7 @@ define void @atomic_fetch_max64(i64 %x) nounwind {
; X64-NEXT: movq %rax, %rcx
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
; X64-NEXT: subq %rdx, %rcx
-; X64-NEXT: cmovgeq %rax, %rdx
+; X64-NEXT: cmovgq %rax, %rdx
; X64-NEXT: lock cmpxchgq %rdx, {{.*}}(%rip)
; X64-NEXT: sete %dl
; X64-NEXT: testb $1, %dl
@@ -404,19 +404,17 @@ define void @atomic_fetch_max64(i64 %x) nounwind {
; I486-NEXT: # =>This Inner Loop Header: Depth=1
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
-; I486-NEXT: movl %ecx, %edx
+; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
+; I486-NEXT: subl %ecx, %edx
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; I486-NEXT: subl %esi, %edx
-; I486-NEXT: movl %eax, %edi
-; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; I486-NEXT: sbbl %ebx, %edi
-; I486-NEXT: movl %ecx, %esi
+; I486-NEXT: sbbl %eax, %esi
+; I486-NEXT: movl %ecx, %edi
; I486-NEXT: movl %eax, %ebx
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; I486-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; I486-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; I486-NEXT: jge .LBB6_4
+; I486-NEXT: jl .LBB6_4
; I486-NEXT: # %bb.3: # %atomicrmw.start
; I486-NEXT: # in Loop: Header=BB6_1 Depth=1
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
diff --git a/llvm/test/CodeGen/X86/atomic6432.ll b/llvm/test/CodeGen/X86/atomic6432.ll
index b45a5bebb566..31cc79536824 100644
--- a/llvm/test/CodeGen/X86/atomic6432.ll
+++ b/llvm/test/CodeGen/X86/atomic6432.ll
@@ -563,21 +563,20 @@ define void @atomic_fetch_max64(i64 %x) nounwind {
; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X32-NEXT: movl %eax, %ecx
+; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X32-NEXT: subl %eax, %ecx
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
-; X32-NEXT: subl %esi, %ecx
-; X32-NEXT: movl %edx, %edi
+; X32-NEXT: sbbl %edx, %esi
+; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
+; X32-NEXT: cmovll %edx, %edi
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
-; X32-NEXT: sbbl %ebx, %edi
-; X32-NEXT: cmovgel %edx, %ebx
-; X32-NEXT: cmovgel %eax, %esi
+; X32-NEXT: cmovll %eax, %ebx
; X32-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X32-NEXT: movl %ebx, %ecx
-; X32-NEXT: movl %esi, %ebx
+; X32-NEXT: movl %edi, %ecx
; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X32-NEXT: movl %edi, (%esp) # 4-byte Spill
+; X32-NEXT: movl %esi, (%esp) # 4-byte Spill
; X32-NEXT: jne .LBB6_1
; X32-NEXT: jmp .LBB6_2
; X32-NEXT: .LBB6_2: # %atomicrmw.end
diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll
index 9960c25f70da..41ebc322b430 100644
--- a/llvm/test/CodeGen/X86/cmov.ll
+++ b/llvm/test/CodeGen/X86/cmov.ll
@@ -212,3 +212,26 @@ define i32 @smin(i32 %x) {
ret i32 %sel
}
+define i32 @pr47049_1(i32 %0) {
+; CHECK-LABEL: pr47049_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: movl $1, %eax
+; CHECK-NEXT: cmovlel %edi, %eax
+; CHECK-NEXT: retq
+ %2 = icmp slt i32 %0, 1
+ %3 = select i1 %2, i32 %0, i32 1
+ ret i32 %3
+}
+
+define i32 @pr47049_2(i32 %0) {
+; CHECK-LABEL: pr47049_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: cmovnsl %edi, %eax
+; CHECK-NEXT: retq
+ %2 = icmp sgt i32 %0, -1
+ %3 = select i1 %2, i32 %0, i32 -1
+ ret i32 %3
+}
diff --git a/llvm/test/CodeGen/X86/pr5145.ll b/llvm/test/CodeGen/X86/pr5145.ll
index cb7e1bc92ae1..582d3276e358 100644
--- a/llvm/test/CodeGen/X86/pr5145.ll
+++ b/llvm/test/CodeGen/X86/pr5145.ll
@@ -9,7 +9,7 @@ define void @atomic_maxmin_i8() {
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpb $4, %al
+; CHECK-NEXT: cmpb $5, %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movl $5, %ecx
; CHECK-NEXT: cmovgl %eax, %ecx
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