[PATCH] D84548: [AArch64][SVE] Add lowering for llvm fceil

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

I've been investigating this area (although related to a different node) and I've had a change of heart.  When lowering the one operand nodes to predicated versions I think we should introduce SVE specific passthru nodes much like DUP but in this case it would be FRINTP_MERGE_PASSTHRU.  This can be used to lower common ISD nodes and SVE intrinsics alike.  My original "use _PRED" comments are only relevant to two and three operand operations where there is an advantage to using _PRED nodes to free up some better register allocation.  One operand operations do not have this problem because the predicate variants have a dedicated output register.  Sorry for the initial misdirection.


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  https://reviews.llvm.org/D84548/new/

https://reviews.llvm.org/D84548