[PATCH] D85530: [AMDGPU] Don't cluster stores

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: rampitec, arsenm, kerbowa, vpykhtin.
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Clustering loads has caching benefits, but as far as I know there is no
advantage to clustering stores on any AMDGPU subtargets.

The disadvantage is that it tends to increase register pressure and
restricts scheduling freedom.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85530

Files:
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
  llvm/test/CodeGen/AMDGPU/cluster_stores.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
  llvm/test/CodeGen/AMDGPU/fshr.ll
  llvm/test/CodeGen/AMDGPU/half.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll
  llvm/test/CodeGen/AMDGPU/merge-stores.ll
  llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  llvm/test/CodeGen/AMDGPU/stack-realign.ll
  llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
  llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll

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