[llvm] 1ffb468 - [NFC][Test] Format the test with script update_llc_test_checks.py
QingShan Zhang via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 03:22:46 PDT 2020
Author: QingShan Zhang
Date: 2020-08-07T10:22:38Z
New Revision: 1ffb468369607e0ccf6e6790965471019dbb7357
URL: https://github.com/llvm/llvm-project/commit/1ffb468369607e0ccf6e6790965471019dbb7357
DIFF: https://github.com/llvm/llvm-project/commit/1ffb468369607e0ccf6e6790965471019dbb7357.diff
LOG: [NFC][Test] Format the test with script update_llc_test_checks.py
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
index 667425d86c69..f0fa9382d00c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
@@ -237,157 +237,157 @@ define amdgpu_kernel void @round_v2f64(<2 x double> addrspace(1)* %out, <2 x dou
define amdgpu_kernel void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) #0 {
; SI-LABEL: round_v4f64:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x11
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_movk_i32 s18, 0xfc01
-; SI-NEXT: s_mov_b32 s3, 0xfffff
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
-; SI-NEXT: s_add_i32 s19, s0, s18
-; SI-NEXT: s_mov_b32 s2, s6
-; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s19
-; SI-NEXT: s_brev_b32 s20, 1
-; SI-NEXT: s_andn2_b64 s[16:17], s[10:11], s[0:1]
-; SI-NEXT: s_and_b32 s0, s11, s20
-; SI-NEXT: v_mov_b32_e32 v1, s0
-; SI-NEXT: v_mov_b32_e32 v0, s17
-; SI-NEXT: v_cmp_lt_i32_e64 vcc, s19, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s11
-; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s19, 51
-; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
-; SI-NEXT: v_mov_b32_e32 v0, s16
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v2, s10
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
-; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
-; SI-NEXT: s_add_i32 s17, s0, s18
-; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
-; SI-NEXT: s_brev_b32 s16, -2
-; SI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
-; SI-NEXT: v_mov_b32_e32 v4, s11
-; SI-NEXT: v_bfi_b32 v4, s16, v12, v4
-; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s17
-; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; SI-NEXT: v_mov_b32_e32 v2, 0
-; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[0:1]
-; SI-NEXT: s_and_b32 s0, s9, s20
-; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
-; SI-NEXT: v_mov_b32_e32 v1, s0
-; SI-NEXT: v_mov_b32_e32 v0, s11
-; SI-NEXT: v_cmp_lt_i32_e64 vcc, s17, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s9
-; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s17, 51
-; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
-; SI-NEXT: v_mov_b32_e32 v0, s10
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v4, s8
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
-; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014
-; SI-NEXT: s_add_i32 s10, s0, s18
-; SI-NEXT: v_mov_b32_e32 v6, s9
-; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s10
-; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
-; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[0:1]
-; SI-NEXT: v_bfi_b32 v6, s16, v12, v6
-; SI-NEXT: s_and_b32 s0, s15, s20
-; SI-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s0
-; SI-NEXT: v_mov_b32_e32 v4, s9
-; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s15
-; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s10, 51
-; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
-; SI-NEXT: v_mov_b32_e32 v4, s8
-; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v6, s14
-; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
-; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
-; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014
-; SI-NEXT: v_mov_b32_e32 v10, s15
-; SI-NEXT: s_add_i32 s8, s0, s18
-; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
-; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s8
-; SI-NEXT: v_bfi_b32 v10, s16, v12, v10
-; SI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
-; SI-NEXT: v_mov_b32_e32 v6, 0
-; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[0:1]
-; SI-NEXT: s_and_b32 s0, s13, s20
-; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
-; SI-NEXT: v_mov_b32_e32 v5, s0
-; SI-NEXT: v_mov_b32_e32 v4, s3
-; SI-NEXT: v_cmp_lt_i32_e64 vcc, s8, 0
-; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s13
-; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s8, 51
-; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
-; SI-NEXT: v_mov_b32_e32 v4, s2
-; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
-; SI-NEXT: v_mov_b32_e32 v10, s12
-; SI-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1]
-; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[4:5]
-; SI-NEXT: v_mov_b32_e32 v13, s13
-; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
-; SI-NEXT: v_bfi_b32 v12, s16, v12, v13
-; SI-NEXT: v_cndmask_b32_e32 v11, 0, v12, vcc
-; SI-NEXT: v_mov_b32_e32 v10, 0
-; SI-NEXT: v_mov_b32_e32 v8, 0
-; SI-NEXT: v_add_f64 v[4:5], v[4:5], v[10:11]
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[8:9]
-; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x11
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_movk_i32 s18, 0xfc01
+; SI-NEXT: s_mov_b32 s3, 0xfffff
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_bfe_u32 s0, s11, 0xb0014
+; SI-NEXT: s_add_i32 s19, s0, s18
+; SI-NEXT: s_mov_b32 s2, s6
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s19
+; SI-NEXT: s_brev_b32 s20, 1
+; SI-NEXT: s_andn2_b64 s[16:17], s[10:11], s[0:1]
+; SI-NEXT: s_and_b32 s0, s11, s20
+; SI-NEXT: v_mov_b32_e32 v1, s0
+; SI-NEXT: v_mov_b32_e32 v0, s17
+; SI-NEXT: v_cmp_lt_i32_e64 vcc, s19, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v1, s11
+; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s19, 51
+; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; SI-NEXT: v_mov_b32_e32 v0, s16
+; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT: v_mov_b32_e32 v2, s10
+; SI-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; SI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
+; SI-NEXT: s_bfe_u32 s0, s9, 0xb0014
+; SI-NEXT: s_add_i32 s17, s0, s18
+; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; SI-NEXT: s_brev_b32 s16, -2
+; SI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
+; SI-NEXT: v_mov_b32_e32 v4, s11
+; SI-NEXT: v_bfi_b32 v4, s16, v12, v4
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s17
+; SI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; SI-NEXT: v_mov_b32_e32 v2, 0
+; SI-NEXT: s_andn2_b64 s[10:11], s[8:9], s[0:1]
+; SI-NEXT: s_and_b32 s0, s9, s20
+; SI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
+; SI-NEXT: v_mov_b32_e32 v1, s0
+; SI-NEXT: v_mov_b32_e32 v0, s11
+; SI-NEXT: v_cmp_lt_i32_e64 vcc, s17, 0
+; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; SI-NEXT: v_mov_b32_e32 v1, s9
+; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s17, 51
+; SI-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1]
+; SI-NEXT: v_mov_b32_e32 v0, s10
+; SI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
+; SI-NEXT: v_mov_b32_e32 v4, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; SI-NEXT: v_add_f64 v[4:5], s[8:9], -v[0:1]
+; SI-NEXT: s_bfe_u32 s0, s15, 0xb0014
+; SI-NEXT: s_add_i32 s10, s0, s18
+; SI-NEXT: v_mov_b32_e32 v6, s9
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s10
+; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; SI-NEXT: s_andn2_b64 s[8:9], s[14:15], s[0:1]
+; SI-NEXT: v_bfi_b32 v6, s16, v12, v6
+; SI-NEXT: s_and_b32 s0, s15, s20
+; SI-NEXT: v_cndmask_b32_e32 v9, 0, v6, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s0
+; SI-NEXT: v_mov_b32_e32 v4, s9
+; SI-NEXT: v_cmp_lt_i32_e64 vcc, s10, 0
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s15
+; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s10, 51
+; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
+; SI-NEXT: v_mov_b32_e32 v4, s8
+; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; SI-NEXT: v_mov_b32_e32 v6, s14
+; SI-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[0:1]
+; SI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
+; SI-NEXT: s_bfe_u32 s0, s13, 0xb0014
+; SI-NEXT: v_mov_b32_e32 v10, s15
+; SI-NEXT: s_add_i32 s8, s0, s18
+; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; SI-NEXT: s_lshr_b64 s[0:1], s[2:3], s8
+; SI-NEXT: v_bfi_b32 v10, s16, v12, v10
+; SI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
+; SI-NEXT: v_mov_b32_e32 v6, 0
+; SI-NEXT: s_andn2_b64 s[2:3], s[12:13], s[0:1]
+; SI-NEXT: s_and_b32 s0, s13, s20
+; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
+; SI-NEXT: v_mov_b32_e32 v5, s0
+; SI-NEXT: v_mov_b32_e32 v4, s3
+; SI-NEXT: v_cmp_lt_i32_e64 vcc, s8, 0
+; SI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT: v_mov_b32_e32 v5, s13
+; SI-NEXT: v_cmp_gt_i32_e64 s[0:1], s8, 51
+; SI-NEXT: v_cndmask_b32_e64 v5, v4, v5, s[0:1]
+; SI-NEXT: v_mov_b32_e32 v4, s2
+; SI-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc
+; SI-NEXT: v_mov_b32_e32 v10, s12
+; SI-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1]
+; SI-NEXT: v_add_f64 v[10:11], s[12:13], -v[4:5]
+; SI-NEXT: v_mov_b32_e32 v13, s13
+; SI-NEXT: v_cmp_ge_f64_e64 vcc, |v[10:11]|, 0.5
+; SI-NEXT: v_bfi_b32 v12, s16, v12, v13
+; SI-NEXT: v_cndmask_b32_e32 v11, 0, v12, vcc
+; SI-NEXT: v_mov_b32_e32 v10, 0
+; SI-NEXT: v_mov_b32_e32 v8, 0
+; SI-NEXT: v_add_f64 v[4:5], v[4:5], v[10:11]
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[8:9]
+; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_endpgm
;
; CI-LABEL: round_v4f64:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x11
-; CI-NEXT: s_brev_b32 s12, -2
-; CI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
-; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
-; CI-NEXT: s_mov_b32 s3, 0xf000
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_trunc_f64_e32 v[0:1], s[6:7]
-; CI-NEXT: v_mov_b32_e32 v4, s7
-; CI-NEXT: v_add_f64 v[2:3], s[6:7], -v[0:1]
-; CI-NEXT: v_bfi_b32 v4, s12, v12, v4
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
-; CI-NEXT: v_trunc_f64_e32 v[8:9], s[4:5]
-; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; CI-NEXT: v_mov_b32_e32 v2, 0
-; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
-; CI-NEXT: v_add_f64 v[0:1], s[4:5], -v[8:9]
-; CI-NEXT: v_mov_b32_e32 v4, s5
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
-; CI-NEXT: v_bfi_b32 v4, s12, v12, v4
-; CI-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
-; CI-NEXT: v_trunc_f64_e32 v[4:5], s[10:11]
-; CI-NEXT: v_mov_b32_e32 v10, s11
-; CI-NEXT: v_add_f64 v[6:7], s[10:11], -v[4:5]
-; CI-NEXT: v_bfi_b32 v10, s12, v12, v10
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
-; CI-NEXT: v_mov_b32_e32 v6, 0
-; CI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
-; CI-NEXT: v_trunc_f64_e32 v[10:11], s[8:9]
-; CI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
-; CI-NEXT: v_add_f64 v[4:5], s[8:9], -v[10:11]
-; CI-NEXT: v_mov_b32_e32 v13, s9
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
-; CI-NEXT: v_bfi_b32 v12, s12, v12, v13
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v12, vcc
-; CI-NEXT: v_mov_b32_e32 v4, 0
-; CI-NEXT: v_mov_b32_e32 v0, 0
-; CI-NEXT: v_add_f64 v[4:5], v[10:11], v[4:5]
-; CI-NEXT: s_mov_b32 s2, -1
-; CI-NEXT: v_add_f64 v[0:1], v[8:9], v[0:1]
-; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
-; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; CI-NEXT: s_endpgm
+; CI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x11
+; CI-NEXT: s_brev_b32 s12, -2
+; CI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
+; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_trunc_f64_e32 v[0:1], s[6:7]
+; CI-NEXT: v_mov_b32_e32 v4, s7
+; CI-NEXT: v_add_f64 v[2:3], s[6:7], -v[0:1]
+; CI-NEXT: v_bfi_b32 v4, s12, v12, v4
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; CI-NEXT: v_trunc_f64_e32 v[8:9], s[4:5]
+; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; CI-NEXT: v_mov_b32_e32 v2, 0
+; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
+; CI-NEXT: v_add_f64 v[0:1], s[4:5], -v[8:9]
+; CI-NEXT: v_mov_b32_e32 v4, s5
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
+; CI-NEXT: v_bfi_b32 v4, s12, v12, v4
+; CI-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
+; CI-NEXT: v_trunc_f64_e32 v[4:5], s[10:11]
+; CI-NEXT: v_mov_b32_e32 v10, s11
+; CI-NEXT: v_add_f64 v[6:7], s[10:11], -v[4:5]
+; CI-NEXT: v_bfi_b32 v10, s12, v12, v10
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
+; CI-NEXT: v_mov_b32_e32 v6, 0
+; CI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
+; CI-NEXT: v_trunc_f64_e32 v[10:11], s[8:9]
+; CI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
+; CI-NEXT: v_add_f64 v[4:5], s[8:9], -v[10:11]
+; CI-NEXT: v_mov_b32_e32 v13, s9
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; CI-NEXT: v_bfi_b32 v12, s12, v12, v13
+; CI-NEXT: v_cndmask_b32_e32 v5, 0, v12, vcc
+; CI-NEXT: v_mov_b32_e32 v4, 0
+; CI-NEXT: v_mov_b32_e32 v0, 0
+; CI-NEXT: v_add_f64 v[4:5], v[10:11], v[4:5]
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: v_add_f64 v[0:1], v[8:9], v[0:1]
+; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; CI-NEXT: s_endpgm
%result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
store <4 x double> %result, <4 x double> addrspace(1)* %out
ret void
@@ -600,82 +600,82 @@ define amdgpu_kernel void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x dou
;
; CI-LABEL: round_v8f64:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19
-; CI-NEXT: s_brev_b32 s2, -2
-; CI-NEXT: v_mov_b32_e32 v16, 0x3ff00000
-; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; CI-NEXT: s_mov_b32 s7, 0xf000
-; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: v_trunc_f64_e32 v[0:1], s[10:11]
-; CI-NEXT: v_mov_b32_e32 v4, s11
-; CI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
-; CI-NEXT: v_bfi_b32 v4, s2, v16, v4
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
-; CI-NEXT: v_mov_b32_e32 v2, 0
-; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; CI-NEXT: v_trunc_f64_e32 v[4:5], s[8:9]
-; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
-; CI-NEXT: v_add_f64 v[0:1], s[8:9], -v[4:5]
-; CI-NEXT: v_mov_b32_e32 v6, s9
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
-; CI-NEXT: v_bfi_b32 v6, s2, v16, v6
-; CI-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc
-; CI-NEXT: v_trunc_f64_e32 v[6:7], s[14:15]
-; CI-NEXT: v_mov_b32_e32 v0, 0
-; CI-NEXT: v_add_f64 v[0:1], v[4:5], v[0:1]
-; CI-NEXT: v_add_f64 v[4:5], s[14:15], -v[6:7]
-; CI-NEXT: v_mov_b32_e32 v8, s15
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
-; CI-NEXT: v_bfi_b32 v8, s2, v16, v8
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
-; CI-NEXT: v_trunc_f64_e32 v[8:9], s[12:13]
-; CI-NEXT: v_mov_b32_e32 v4, 0
-; CI-NEXT: v_add_f64 v[6:7], v[6:7], v[4:5]
-; CI-NEXT: v_add_f64 v[4:5], s[12:13], -v[8:9]
-; CI-NEXT: v_mov_b32_e32 v10, s13
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
-; CI-NEXT: v_bfi_b32 v10, s2, v16, v10
-; CI-NEXT: v_cndmask_b32_e32 v5, 0, v10, vcc
-; CI-NEXT: v_mov_b32_e32 v4, 0
-; CI-NEXT: v_add_f64 v[4:5], v[8:9], v[4:5]
-; CI-NEXT: v_mov_b32_e32 v8, s19
-; CI-NEXT: v_bfi_b32 v18, s2, v16, v8
-; CI-NEXT: v_trunc_f64_e32 v[8:9], s[20:21]
-; CI-NEXT: v_trunc_f64_e32 v[10:11], s[22:23]
-; CI-NEXT: v_add_f64 v[14:15], s[20:21], -v[8:9]
-; CI-NEXT: v_mov_b32_e32 v19, s23
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
-; CI-NEXT: v_add_f64 v[14:15], s[22:23], -v[10:11]
-; CI-NEXT: v_mov_b32_e32 v17, s21
-; CI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
-; CI-NEXT: v_bfi_b32 v19, s2, v16, v19
-; CI-NEXT: v_trunc_f64_e32 v[12:13], s[16:17]
-; CI-NEXT: v_bfi_b32 v17, s2, v16, v17
-; CI-NEXT: v_cndmask_b32_e64 v15, 0, v19, s[0:1]
-; CI-NEXT: v_mov_b32_e32 v14, 0
-; CI-NEXT: v_add_f64 v[10:11], v[10:11], v[14:15]
-; CI-NEXT: v_cndmask_b32_e32 v15, 0, v17, vcc
-; CI-NEXT: v_mov_b32_e32 v14, 0
-; CI-NEXT: v_mov_b32_e32 v17, s17
-; CI-NEXT: v_add_f64 v[8:9], v[8:9], v[14:15]
-; CI-NEXT: v_add_f64 v[14:15], s[16:17], -v[12:13]
-; CI-NEXT: v_bfi_b32 v19, s2, v16, v17
-; CI-NEXT: v_trunc_f64_e32 v[16:17], s[18:19]
-; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
-; CI-NEXT: v_add_f64 v[14:15], s[18:19], -v[16:17]
-; CI-NEXT: s_mov_b32 s6, -1
-; CI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
-; CI-NEXT: v_mov_b32_e32 v14, 0
-; CI-NEXT: v_cndmask_b32_e64 v15, 0, v18, s[0:1]
-; CI-NEXT: v_add_f64 v[14:15], v[16:17], v[14:15]
-; CI-NEXT: v_cndmask_b32_e32 v17, 0, v19, vcc
-; CI-NEXT: v_mov_b32_e32 v16, 0
-; CI-NEXT: v_add_f64 v[12:13], v[12:13], v[16:17]
-; CI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
-; CI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
-; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
-; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; CI-NEXT: s_endpgm
+; CI-NEXT: s_load_dwordx16 s[8:23], s[0:1], 0x19
+; CI-NEXT: s_brev_b32 s2, -2
+; CI-NEXT: v_mov_b32_e32 v16, 0x3ff00000
+; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_trunc_f64_e32 v[0:1], s[10:11]
+; CI-NEXT: v_mov_b32_e32 v4, s11
+; CI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
+; CI-NEXT: v_bfi_b32 v4, s2, v16, v4
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
+; CI-NEXT: v_mov_b32_e32 v2, 0
+; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
+; CI-NEXT: v_trunc_f64_e32 v[4:5], s[8:9]
+; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
+; CI-NEXT: v_add_f64 v[0:1], s[8:9], -v[4:5]
+; CI-NEXT: v_mov_b32_e32 v6, s9
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
+; CI-NEXT: v_bfi_b32 v6, s2, v16, v6
+; CI-NEXT: v_cndmask_b32_e32 v1, 0, v6, vcc
+; CI-NEXT: v_trunc_f64_e32 v[6:7], s[14:15]
+; CI-NEXT: v_mov_b32_e32 v0, 0
+; CI-NEXT: v_add_f64 v[0:1], v[4:5], v[0:1]
+; CI-NEXT: v_add_f64 v[4:5], s[14:15], -v[6:7]
+; CI-NEXT: v_mov_b32_e32 v8, s15
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; CI-NEXT: v_bfi_b32 v8, s2, v16, v8
+; CI-NEXT: v_cndmask_b32_e32 v5, 0, v8, vcc
+; CI-NEXT: v_trunc_f64_e32 v[8:9], s[12:13]
+; CI-NEXT: v_mov_b32_e32 v4, 0
+; CI-NEXT: v_add_f64 v[6:7], v[6:7], v[4:5]
+; CI-NEXT: v_add_f64 v[4:5], s[12:13], -v[8:9]
+; CI-NEXT: v_mov_b32_e32 v10, s13
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
+; CI-NEXT: v_bfi_b32 v10, s2, v16, v10
+; CI-NEXT: v_cndmask_b32_e32 v5, 0, v10, vcc
+; CI-NEXT: v_mov_b32_e32 v4, 0
+; CI-NEXT: v_add_f64 v[4:5], v[8:9], v[4:5]
+; CI-NEXT: v_mov_b32_e32 v8, s19
+; CI-NEXT: v_bfi_b32 v18, s2, v16, v8
+; CI-NEXT: v_trunc_f64_e32 v[8:9], s[20:21]
+; CI-NEXT: v_trunc_f64_e32 v[10:11], s[22:23]
+; CI-NEXT: v_add_f64 v[14:15], s[20:21], -v[8:9]
+; CI-NEXT: v_mov_b32_e32 v19, s23
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
+; CI-NEXT: v_add_f64 v[14:15], s[22:23], -v[10:11]
+; CI-NEXT: v_mov_b32_e32 v17, s21
+; CI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
+; CI-NEXT: v_bfi_b32 v19, s2, v16, v19
+; CI-NEXT: v_trunc_f64_e32 v[12:13], s[16:17]
+; CI-NEXT: v_bfi_b32 v17, s2, v16, v17
+; CI-NEXT: v_cndmask_b32_e64 v15, 0, v19, s[0:1]
+; CI-NEXT: v_mov_b32_e32 v14, 0
+; CI-NEXT: v_add_f64 v[10:11], v[10:11], v[14:15]
+; CI-NEXT: v_cndmask_b32_e32 v15, 0, v17, vcc
+; CI-NEXT: v_mov_b32_e32 v14, 0
+; CI-NEXT: v_mov_b32_e32 v17, s17
+; CI-NEXT: v_add_f64 v[8:9], v[8:9], v[14:15]
+; CI-NEXT: v_add_f64 v[14:15], s[16:17], -v[12:13]
+; CI-NEXT: v_bfi_b32 v19, s2, v16, v17
+; CI-NEXT: v_trunc_f64_e32 v[16:17], s[18:19]
+; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[14:15]|, 0.5
+; CI-NEXT: v_add_f64 v[14:15], s[18:19], -v[16:17]
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: v_cmp_ge_f64_e64 s[0:1], |v[14:15]|, 0.5
+; CI-NEXT: v_mov_b32_e32 v14, 0
+; CI-NEXT: v_cndmask_b32_e64 v15, 0, v18, s[0:1]
+; CI-NEXT: v_add_f64 v[14:15], v[16:17], v[14:15]
+; CI-NEXT: v_cndmask_b32_e32 v17, 0, v19, vcc
+; CI-NEXT: v_mov_b32_e32 v16, 0
+; CI-NEXT: v_add_f64 v[12:13], v[12:13], v[16:17]
+; CI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:48
+; CI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:32
+; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; CI-NEXT: s_endpgm
%result = call <8 x double> @llvm.round.v8f64(<8 x double> %in) #1
store <8 x double> %result, <8 x double> addrspace(1)* %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
index f423672b8da5..07c2575ab422 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
@@ -11,27 +11,27 @@
define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
; SI-LABEL: sgpr_if_else_salu_br:
; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
-; SI-NEXT: s_load_dword s0, s[0:1], 0xf
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_cmp_lg_u32 s8, 0
-; SI-NEXT: s_cbranch_scc0 BB0_2
-; SI-NEXT:; %bb.1: ; %else
-; SI-NEXT: s_add_i32 s0, s11, s0
-; SI-NEXT: s_cbranch_execz BB0_3
-; SI-NEXT: s_branch BB0_4
-; SI-NEXT:BB0_2:
-; SI-NEXT: ; implicit-def: $sgpr0
-; SI-NEXT:BB0_3: ; %if
-; SI-NEXT: s_sub_i32 s0, s9, s10
-; SI-NEXT:BB0_4: ; %endif
-; SI-NEXT: s_add_i32 s0, s0, s8
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
+; SI-NEXT: s_load_dword s0, s[0:1], 0xf
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s8, 0
+; SI-NEXT: s_cbranch_scc0 BB0_2
+; SI-NEXT: ; %bb.1: ; %else
+; SI-NEXT: s_add_i32 s0, s11, s0
+; SI-NEXT: s_cbranch_execz BB0_3
+; SI-NEXT: s_branch BB0_4
+; SI-NEXT: BB0_2:
+; SI-NEXT: ; implicit-def: $sgpr0
+; SI-NEXT: BB0_3: ; %if
+; SI-NEXT: s_sub_i32 s0, s9, s10
+; SI-NEXT: BB0_4: ; %endif
+; SI-NEXT: s_add_i32 s0, s0, s8
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
entry:
%0 = icmp eq i32 %a, 0
@@ -55,32 +55,32 @@ endif:
define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
; SI-LABEL: sgpr_if_else_salu_br_opt:
; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dword s2, s[0:1], 0x13
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_cmp_lg_u32 s2, 0
-; SI-NEXT: s_cbranch_scc0 BB1_2
-; SI-NEXT:; %bb.1: ; %else
-; SI-NEXT: s_load_dword s3, s[0:1], 0x2e
-; SI-NEXT: s_load_dword s6, s[0:1], 0x37
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_add_i32 s3, s3, s6
-; SI-NEXT: s_cbranch_execz BB1_3
-; SI-NEXT: s_branch BB1_4
-; SI-NEXT:BB1_2:
-; SI-NEXT: ; implicit-def: $sgpr3
-; SI-NEXT:BB1_3: ; %if
-; SI-NEXT: s_load_dword s3, s[0:1], 0x1c
-; SI-NEXT: s_load_dword s0, s[0:1], 0x25
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_add_i32 s3, s3, s0
-; SI-NEXT:BB1_4: ; %endif
-; SI-NEXT: s_add_i32 s0, s3, s2
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dword s2, s[0:1], 0x13
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s2, 0
+; SI-NEXT: s_cbranch_scc0 BB1_2
+; SI-NEXT: ; %bb.1: ; %else
+; SI-NEXT: s_load_dword s3, s[0:1], 0x2e
+; SI-NEXT: s_load_dword s6, s[0:1], 0x37
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_add_i32 s3, s3, s6
+; SI-NEXT: s_cbranch_execz BB1_3
+; SI-NEXT: s_branch BB1_4
+; SI-NEXT: BB1_2:
+; SI-NEXT: ; implicit-def: $sgpr3
+; SI-NEXT: BB1_3: ; %if
+; SI-NEXT: s_load_dword s3, s[0:1], 0x1c
+; SI-NEXT: s_load_dword s0, s[0:1], 0x25
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_add_i32 s3, s3, s0
+; SI-NEXT: BB1_4: ; %endif
+; SI-NEXT: s_add_i32 s0, s3, s2
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
entry:
%cmp0 = icmp eq i32 %a, 0
More information about the llvm-commits
mailing list