[PATCH] D84732: [RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.

[Hsiangkai Wang via Phabricator via llvm-commits]

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Fix problems when rebasing.


HsiangKai added a comment.

Apply clang-format.


Implement `vmsge{u}.vx` pseudo instruction.

According to RISC-V V specification, there are different scenarios for this pseudo instruction. I list them below.

  unmasked va >= x
  
    pseudoinstruction: vmsge{u}.vx vd, va, x
    expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
  
  masked va >= x, vd != v0
  
    pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
    expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
  
  masked va >= x, vd == v0
  
    pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
    expansion: vmslt{u}.vx vt, va, x;  vmandnot.mm vd, vd, vt

Use pseudo instruction to model `vmsge{u}.vx`. The pseudo instruction will convert to different expansion according to the condition.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D84732

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/compare.s

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