[llvm] f92e0d9 - [VE] Optimize trunc related instructions
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 6 17:21:17 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-08-07T09:21:05+09:00
New Revision: f92e0d9384763913a745cbe9c757fbb40691dcd1
URL: https://github.com/llvm/llvm-project/commit/f92e0d9384763913a745cbe9c757fbb40691dcd1
DIFF: https://github.com/llvm/llvm-project/commit/f92e0d9384763913a745cbe9c757fbb40691dcd1.diff
LOG: [VE] Optimize trunc related instructions
Change to not generate truncate instructions if all use of a truncate
operation don't care about higher bits. For example, an i32 add
instruction doesn't care about higher 32 bits in 64 bit registers.
Updates regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D85418
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
llvm/test/CodeGen/VE/addition.ll
llvm/test/CodeGen/VE/bitcast.ll
llvm/test/CodeGen/VE/branch1.ll
llvm/test/CodeGen/VE/bswap.ll
llvm/test/CodeGen/VE/cast.ll
llvm/test/CodeGen/VE/div.ll
llvm/test/CodeGen/VE/int_to_fp.ll
llvm/test/CodeGen/VE/left_shift.ll
llvm/test/CodeGen/VE/max.ll
llvm/test/CodeGen/VE/min.ll
llvm/test/CodeGen/VE/multiply.ll
llvm/test/CodeGen/VE/rem.ll
llvm/test/CodeGen/VE/right_shift.ll
llvm/test/CodeGen/VE/rotl.ll
llvm/test/CodeGen/VE/rotr.ll
llvm/test/CodeGen/VE/select.ll
llvm/test/CodeGen/VE/selectccf32c.ll
llvm/test/CodeGen/VE/selectccf64c.ll
llvm/test/CodeGen/VE/selectcci32.ll
llvm/test/CodeGen/VE/selectcci32c.ll
llvm/test/CodeGen/VE/selectcci32i.ll
llvm/test/CodeGen/VE/selectcci64c.ll
llvm/test/CodeGen/VE/setcci32.ll
llvm/test/CodeGen/VE/setcci32i.ll
llvm/test/CodeGen/VE/subtraction.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index e2232f4500e3..e045899a1ec9 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -703,6 +703,9 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
setStackPointerRegisterToSaveRestore(VE::SX11);
+ // We have target-specific dag combine patterns for the following nodes:
+ setTargetDAGCombine(ISD::TRUNCATE);
+
// Set function alignment to 16 bytes
setMinFunctionAlignment(Align(16));
@@ -1026,3 +1029,130 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
}
}
/// } Custom Lower
+
+static bool isI32Insn(const SDNode *User, const SDNode *N) {
+ switch (User->getOpcode()) {
+ default:
+ return false;
+ case ISD::ADD:
+ case ISD::SUB:
+ case ISD::MUL:
+ case ISD::SDIV:
+ case ISD::UDIV:
+ case ISD::SETCC:
+ case ISD::SMIN:
+ case ISD::SMAX:
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::BSWAP:
+ case ISD::SINT_TO_FP:
+ case ISD::UINT_TO_FP:
+ case ISD::BR_CC:
+ case ISD::BITCAST:
+ case ISD::ATOMIC_CMP_SWAP:
+ case ISD::ATOMIC_SWAP:
+ return true;
+ case ISD::SRL:
+ if (N->getOperand(0).getOpcode() != ISD::SRL)
+ return true;
+ // (srl (trunc (srl ...))) may be optimized by combining srl, so
+ // doesn't optimize trunc now.
+ return false;
+ case ISD::SELECT_CC:
+ if (User->getOperand(2).getNode() != N &&
+ User->getOperand(3).getNode() != N)
+ return true;
+ LLVM_FALLTHROUGH;
+ case ISD::AND:
+ case ISD::OR:
+ case ISD::XOR:
+ case ISD::SELECT:
+ case ISD::CopyToReg:
+ // Check all use of selections, bit operations, and copies. If all of them
+ // are safe, optimize truncate to extract_subreg.
+ for (SDNode::use_iterator UI = User->use_begin(), UE = User->use_end();
+ UI != UE; ++UI) {
+ switch ((*UI)->getOpcode()) {
+ default:
+ // If the use is an instruction which treats the source operand as i32,
+ // it is safe to avoid truncate here.
+ if (isI32Insn(*UI, N))
+ continue;
+ break;
+ case ISD::ANY_EXTEND:
+ case ISD::SIGN_EXTEND:
+ case ISD::ZERO_EXTEND: {
+ // Special optimizations to the combination of ext and trunc.
+ // (ext ... (select ... (trunc ...))) is safe to avoid truncate here
+ // since this truncate instruction clears higher 32 bits which is filled
+ // by one of ext instructions later.
+ assert(N->getValueType(0) == MVT::i32 &&
+ "find truncate to not i32 integer");
+ if (User->getOpcode() == ISD::SELECT_CC ||
+ User->getOpcode() == ISD::SELECT)
+ continue;
+ break;
+ }
+ }
+ return false;
+ }
+ return true;
+ }
+}
+
+// Optimize TRUNCATE in DAG combining. Optimizing it in CUSTOM lower is
+// sometime too early. Optimizing it in DAG pattern matching in VEInstrInfo.td
+// is sometime too late. So, doing it at here.
+SDValue VETargetLowering::combineTRUNCATE(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ assert(N->getOpcode() == ISD::TRUNCATE &&
+ "Should be called with a TRUNCATE node");
+
+ SelectionDAG &DAG = DCI.DAG;
+ SDLoc DL(N);
+ EVT VT = N->getValueType(0);
+
+ // We prefer to do this when all types are legal.
+ if (!DCI.isAfterLegalizeDAG())
+ return SDValue();
+
+ // Skip combine TRUNCATE atm if the operand of TRUNCATE might be a constant.
+ if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC &&
+ isa<ConstantSDNode>(N->getOperand(0)->getOperand(0)) &&
+ isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
+ return SDValue();
+
+ // Check all use of this TRUNCATE.
+ for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE;
+ ++UI) {
+ SDNode *User = *UI;
+
+ // Make sure that we're not going to replace TRUNCATE for non i32
+ // instructions.
+ //
+ // FIXME: Although we could sometimes handle this, and it does occur in
+ // practice that one of the condition inputs to the select is also one of
+ // the outputs, we currently can't deal with this.
+ if (isI32Insn(User, N))
+ continue;
+
+ return SDValue();
+ }
+
+ SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32);
+ return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT,
+ N->getOperand(0), SubI32),
+ 0);
+}
+
+SDValue VETargetLowering::PerformDAGCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ switch (N->getOpcode()) {
+ default:
+ break;
+ case ISD::TRUNCATE:
+ return combineTRUNCATE(N, DCI);
+ }
+
+ return SDValue();
+}
diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h
index 4633220efaa1..cd24cbfe5161 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -86,6 +86,12 @@ class VETargetLowering : public TargetLowering {
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
/// } Custom Lower
+ /// Custom DAGCombine {
+ SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+
+ SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
+ /// } Custom DAGCombine
+
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/VE/addition.ll b/llvm/test/CodeGen/VE/addition.ll
index 54275e9e0e26..783bb275d5e1 100644
--- a/llvm/test/CodeGen/VE/addition.ll
+++ b/llvm/test/CodeGen/VE/addition.ll
@@ -3,8 +3,6 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -16,8 +14,6 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -29,8 +25,6 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i32 %1, %0
@@ -49,8 +43,6 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -61,8 +53,6 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -73,8 +63,6 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: adds.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i32 %1, %0
@@ -93,7 +81,6 @@ define i64 @func9(i64 %0, i64 %1) {
define signext i8 @func13(i8 signext %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -105,7 +92,6 @@ define signext i8 @func13(i8 signext %0) {
define signext i16 @func14(i16 signext %0) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -117,7 +103,6 @@ define signext i16 @func14(i16 signext %0) {
define i32 @func15(i32 %0) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%2 = add nsw i32 %0, 5
@@ -136,7 +121,6 @@ define i64 @func16(i64 %0) {
define zeroext i8 @func18(i8 zeroext %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -147,7 +131,6 @@ define zeroext i8 @func18(i8 zeroext %0) {
define zeroext i16 @func19(i16 zeroext %0) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -158,7 +141,6 @@ define zeroext i16 @func19(i16 zeroext %0) {
define i32 @func20(i32 %0) {
; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%2 = add i32 %0, 5
diff --git a/llvm/test/CodeGen/VE/bitcast.ll b/llvm/test/CodeGen/VE/bitcast.ll
index d7c09cd46b61..355ea84ef939 100644
--- a/llvm/test/CodeGen/VE/bitcast.ll
+++ b/llvm/test/CodeGen/VE/bitcast.ll
@@ -22,7 +22,6 @@ define dso_local double @bitcastl2d(i64 %x) {
define dso_local float @bitcastw2f(i32 %x) {
; CHECK-LABEL: bitcastw2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sll %s0, %s0, 32
; CHECK-NEXT: or %s11, 0, %s9
%r = bitcast i32 %x to float
diff --git a/llvm/test/CodeGen/VE/branch1.ll b/llvm/test/CodeGen/VE/branch1.ll
index 5561284c992e..a00102aa838c 100644
--- a/llvm/test/CodeGen/VE/branch1.ll
+++ b/llvm/test/CodeGen/VE/branch1.ll
@@ -3,8 +3,6 @@
define signext i8 @func1(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
@@ -39,8 +37,6 @@ declare i32 @ret(i32)
define i32 @func2(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
@@ -70,8 +66,6 @@ join:
define i32 @func3(i32 %a, i32 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: brle.w %s0, %s1, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2: # %on.true
; CHECK-NEXT: lea %s0, ret at lo
@@ -130,8 +124,6 @@ join:
define i32 @func5(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2: # %on.true
@@ -162,8 +154,6 @@ join:
define i32 @func6(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2: # %on.true
@@ -194,8 +184,6 @@ join:
define i32 @func7(i32 %a, i32 %b) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_5:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
; CHECK-NEXT: brle.w 0, %s0, .LBB{{[0-9]+}}_1
; CHECK-NEXT: # %bb.2: # %on.true
diff --git a/llvm/test/CodeGen/VE/bswap.ll b/llvm/test/CodeGen/VE/bswap.ll
index 39569d8889c5..d87f3c93cb22 100644
--- a/llvm/test/CodeGen/VE/bswap.ll
+++ b/llvm/test/CodeGen/VE/bswap.ll
@@ -14,7 +14,6 @@ declare i64 @llvm.bswap.i64(i64)
define i32 @func2(i32 %p) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.bswap.i32(i32 %p)
@@ -26,7 +25,6 @@ declare i32 @llvm.bswap.i32(i32)
define signext i16 @func3(i16 signext %p) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16
@@ -51,7 +49,6 @@ define i64 @func4(i64 %p) {
define i32 @func5(i32 %p) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.bswap.i32(i32 %p)
@@ -61,7 +58,6 @@ define i32 @func5(i32 %p) {
define zeroext i16 @func6(i16 zeroext %p) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: bswp %s0, %s0, 1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 16
diff --git a/llvm/test/CodeGen/VE/cast.ll b/llvm/test/CodeGen/VE/cast.ll
index 07ad969a1bd3..eccdb7d107c7 100644
--- a/llvm/test/CodeGen/VE/cast.ll
+++ b/llvm/test/CodeGen/VE/cast.ll
@@ -503,7 +503,6 @@ define i64 @i2ull(i32 %0) {
define float @i2f(i32 %x) {
; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i32 %x to float
@@ -513,7 +512,6 @@ define float @i2f(i32 %x) {
define double @i2d(i32 %x) {
; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i32 %x to double
@@ -680,7 +678,6 @@ define i64 @s2ull(i16 signext %0) {
define float @s2f(i16 signext %x) {
; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i16 %x to float
@@ -690,7 +687,6 @@ define float @s2f(i16 signext %x) {
define double @s2d(i16 signext %x) {
; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i16 %x to double
@@ -767,7 +763,6 @@ define i64 @us2ull(i16 zeroext %0) {
define float @us2f(i16 zeroext %x) {
; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i16 %x to float
@@ -777,7 +772,6 @@ define float @us2f(i16 zeroext %x) {
define double @us2d(i16 zeroext %x) {
; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i16 %x to double
@@ -851,7 +845,6 @@ define i64 @c2ull(i8 signext %0) {
define float @c2f(i8 signext %x) {
; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i8 %x to float
@@ -861,7 +854,6 @@ define float @c2f(i8 signext %x) {
define double @c2d(i8 signext %x) {
; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = sitofp i8 %x to double
@@ -935,7 +927,6 @@ define i64 @uc2ull(i8 zeroext %0) {
define float @uc2f(i8 zeroext %x) {
; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i8 %x to float
@@ -945,7 +936,6 @@ define float @uc2f(i8 zeroext %x) {
define double @uc2d(i8 zeroext %x) {
; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = uitofp i8 %x to double
diff --git a/llvm/test/CodeGen/VE/div.ll b/llvm/test/CodeGen/VE/div.ll
index ed434a9a3c7b..b1f5fdf5c5a9 100644
--- a/llvm/test/CodeGen/VE/div.ll
+++ b/llvm/test/CodeGen/VE/div.ll
@@ -14,8 +14,6 @@ define i64 @divi64(i64 %a, i64 %b) {
define i32 @divi32(i32 %a, i32 %b) {
; CHECK-LABEL: divi32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 %a, %b
@@ -36,8 +34,6 @@ define i64 @divu64(i64 %a, i64 %b) {
define i32 @divu32(i32 %a, i32 %b) {
; CHECK-LABEL: divu32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 %a, %b
@@ -48,8 +44,6 @@ define i32 @divu32(i32 %a, i32 %b) {
define signext i16 @divi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: divi16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -65,8 +59,6 @@ define signext i16 @divi16(i16 signext %a, i16 signext %b) {
define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: divu16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
@@ -78,8 +70,6 @@ define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
define signext i8 @divi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: divi8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -95,8 +85,6 @@ define signext i8 @divi8(i8 signext %a, i8 signext %b) {
define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: divu8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
@@ -118,7 +106,6 @@ define i64 @divi64ri(i64 %a, i64 %b) {
define i32 @divi32ri(i32 %a, i32 %b) {
; CHECK-LABEL: divi32ri:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 %a, 3
@@ -139,7 +126,6 @@ define i64 @divu64ri(i64 %a, i64 %b) {
define i32 @divu32ri(i32 %a, i32 %b) {
; CHECK-LABEL: divu32ri:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s0, %s0, (62)0
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 %a, 3
@@ -160,8 +146,7 @@ define i64 @divi64li(i64 %a, i64 %b) {
define i32 @divi32li(i32 %a, i32 %b) {
; CHECK-LABEL: divi32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: divs.w.sx %s0, 3, %s0
+; CHECK-NEXT: divs.w.sx %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = sdiv i32 3, %b
ret i32 %r
@@ -181,8 +166,7 @@ define i64 @divu64li(i64 %a, i64 %b) {
define i32 @divu32li(i32 %a, i32 %b) {
; CHECK-LABEL: divu32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: divu.w %s0, 3, %s0
+; CHECK-NEXT: divu.w %s0, 3, %s1
; CHECK-NEXT: or %s11, 0, %s9
%r = udiv i32 3, %b
ret i32 %r
diff --git a/llvm/test/CodeGen/VE/int_to_fp.ll b/llvm/test/CodeGen/VE/int_to_fp.ll
index 2e850142e2e9..7489f1594dd3 100644
--- a/llvm/test/CodeGen/VE/int_to_fp.ll
+++ b/llvm/test/CodeGen/VE/int_to_fp.ll
@@ -4,7 +4,6 @@
define float @c2f(i8 signext %a) {
; CHECK-LABEL: c2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -16,7 +15,6 @@ entry:
define float @s2f(i16 signext %a) {
; CHECK-LABEL: s2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -28,7 +26,6 @@ entry:
define float @i2f(i32 %a) {
; CHECK-LABEL: i2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -52,7 +49,6 @@ entry:
define float @uc2f(i8 zeroext %a) {
; CHECK-LABEL: uc2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -64,7 +60,6 @@ entry:
define float @us2f(i16 zeroext %a) {
; CHECK-LABEL: us2f:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.s.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -111,7 +106,6 @@ entry:
define double @c2d(i8 signext %a) {
; CHECK-LABEL: c2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -123,7 +117,6 @@ entry:
define double @s2d(i16 signext %a) {
; CHECK-LABEL: s2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -135,7 +128,6 @@ entry:
define double @i2d(i32 %a) {
; CHECK-LABEL: i2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -158,7 +150,6 @@ entry:
define double @uc2d(i8 zeroext %a) {
; CHECK-LABEL: uc2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
@@ -170,7 +161,6 @@ entry:
define double @us2d(i16 zeroext %a) {
; CHECK-LABEL: us2d:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cvt.d.w %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
entry:
diff --git a/llvm/test/CodeGen/VE/left_shift.ll b/llvm/test/CodeGen/VE/left_shift.ll
index fa595a916e52..9479cc793438 100644
--- a/llvm/test/CodeGen/VE/left_shift.ll
+++ b/llvm/test/CodeGen/VE/left_shift.ll
@@ -3,8 +3,6 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -19,8 +17,6 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -35,8 +31,6 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i32 %0, %1
@@ -46,7 +40,6 @@ define i32 @func3(i32 %0, i32 %1) {
define i64 @func4(i64 %0, i64 %1) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i64 %0, %1
@@ -56,8 +49,6 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -71,8 +62,6 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -86,8 +75,6 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i32 %0, %1
@@ -97,7 +84,6 @@ define i32 @func8(i32 %0, i32 %1) {
define i64 @func9(i64 %0, i64 %1) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: sll %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = shl i64 %0, %1
@@ -107,7 +93,6 @@ define i64 @func9(i64 %0, i64 %1) {
define signext i8 @func11(i8 signext %0) {
; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -119,7 +104,6 @@ define signext i8 @func11(i8 signext %0) {
define signext i16 @func12(i16 signext %0) {
; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -131,7 +115,6 @@ define signext i16 @func12(i16 signext %0) {
define i32 @func13(i32 %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i32 %0, 5
@@ -150,7 +133,6 @@ define i64 @func14(i64 %0) {
define zeroext i8 @func16(i8 zeroext %0) {
; CHECK-LABEL: func16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: lea %s1, 224
; CHECK-NEXT: and %s0, %s0, %s1
@@ -162,7 +144,6 @@ define zeroext i8 @func16(i8 zeroext %0) {
define zeroext i16 @func17(i16 zeroext %0) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: lea %s1, 65504
; CHECK-NEXT: and %s0, %s0, %s1
@@ -174,7 +155,6 @@ define zeroext i16 @func17(i16 zeroext %0) {
define i32 @func18(i32 %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
%2 = shl i32 %0, 5
diff --git a/llvm/test/CodeGen/VE/max.ll b/llvm/test/CodeGen/VE/max.ll
index 2c342faa1f05..14f5baba2a14 100644
--- a/llvm/test/CodeGen/VE/max.ll
+++ b/llvm/test/CodeGen/VE/max.ll
@@ -137,8 +137,6 @@ define i64 @max2u64(i64, i64) {
define i32 @maxi32(i32, i32) {
; CHECK-LABEL: maxi32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i32 %0, %1
@@ -149,8 +147,6 @@ define i32 @maxi32(i32, i32) {
define i32 @max2i32(i32, i32) {
; CHECK-LABEL: max2i32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i32 %0, %1
@@ -161,10 +157,9 @@ define i32 @max2i32(i32, i32) {
define i32 @maxu32(i32, i32) {
; CHECK-LABEL: maxu32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s2, %s0
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s2, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
+; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
@@ -174,10 +169,9 @@ define i32 @maxu32(i32, i32) {
define i32 @max2u32(i32, i32) {
; CHECK-LABEL: max2u32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s2, %s0
-; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s2, %s0, %s1
+; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
+; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
diff --git a/llvm/test/CodeGen/VE/min.ll b/llvm/test/CodeGen/VE/min.ll
index dd6ad8460c80..be9f962a8a3d 100644
--- a/llvm/test/CodeGen/VE/min.ll
+++ b/llvm/test/CodeGen/VE/min.ll
@@ -135,8 +135,6 @@ define i64 @min2u64(i64, i64) {
define i32 @mini32(i32, i32) {
; CHECK-LABEL: mini32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i32 %0, %1
@@ -147,8 +145,6 @@ define i32 @mini32(i32, i32) {
define i32 @min2i32(i32, i32) {
; CHECK-LABEL: min2i32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: mins.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i32 %0, %1
@@ -159,10 +155,9 @@ define i32 @min2i32(i32, i32) {
define i32 @minu32(i32, i32) {
; CHECK-LABEL: minu32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s2, %s0
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s2, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
+; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
@@ -172,10 +167,9 @@ define i32 @minu32(i32, i32) {
define i32 @min2u32(i32, i32) {
; CHECK-LABEL: min2u32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s2, %s0
-; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s2, %s0, %s1
+; CHECK-NEXT: cmov.w.le %s1, %s0, %s2
+; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i32 %0, %1
%4 = select i1 %3, i32 %0, i32 %1
@@ -185,8 +179,6 @@ define i32 @min2u32(i32, i32) {
define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {
; CHECK-LABEL: mini1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: and %s2, %s1, %s0
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
diff --git a/llvm/test/CodeGen/VE/multiply.ll b/llvm/test/CodeGen/VE/multiply.ll
index 83b7a67ff453..cfff4c70cd37 100644
--- a/llvm/test/CodeGen/VE/multiply.ll
+++ b/llvm/test/CodeGen/VE/multiply.ll
@@ -3,8 +3,6 @@
define signext i8 @func1(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -16,8 +14,6 @@ define signext i8 @func1(i8 signext %a, i8 signext %b) {
define signext i16 @func2(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -29,8 +25,6 @@ define signext i16 @func2(i16 signext %a, i16 signext %b) {
define i32 @func3(i32 %a, i32 %b) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i32 %b, %a
@@ -49,8 +43,6 @@ define i64 @func4(i64 %a, i64 %b) {
define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -61,8 +53,6 @@ define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -73,8 +63,6 @@ define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
define i32 @func7(i32 %a, i32 %b) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i32 %b, %a
@@ -93,7 +81,6 @@ define i64 @func8(i64 %a, i64 %b) {
define signext i8 @func9(i8 signext %a) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -105,7 +92,6 @@ define signext i8 @func9(i8 signext %a) {
define signext i16 @func10(i16 signext %a) {
; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -117,7 +103,6 @@ define signext i16 @func10(i16 signext %a) {
define i32 @func11(i32 %a) {
; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul nsw i32 %a, 5
@@ -136,7 +121,6 @@ define i64 @func12(i64 %a) {
define zeroext i8 @func13(i8 zeroext %a) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -147,7 +131,6 @@ define zeroext i8 @func13(i8 zeroext %a) {
define zeroext i16 @func14(i16 zeroext %a) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -158,7 +141,6 @@ define zeroext i16 @func14(i16 zeroext %a) {
define i32 @func15(i32 %a) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: muls.w.sx %s0, 5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = mul i32 %a, 5
@@ -177,7 +159,6 @@ define i64 @func16(i64 %a) {
define i32 @func17(i32 %a) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
%r = shl i32 %a, 31
diff --git a/llvm/test/CodeGen/VE/rem.ll b/llvm/test/CodeGen/VE/rem.ll
index 52ac3c3a3c9e..57e07827ed9e 100644
--- a/llvm/test/CodeGen/VE/rem.ll
+++ b/llvm/test/CodeGen/VE/rem.ll
@@ -16,8 +16,6 @@ define i64 @remi64(i64 %a, i64 %b) {
define i32 @remi32(i32 %a, i32 %b) {
; CHECK-LABEL: remi32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -42,8 +40,6 @@ define i64 @remu64(i64 %a, i64 %b) {
define i32 @remu32(i32 %a, i32 %b) {
; CHECK-LABEL: remu32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -56,8 +52,6 @@ define i32 @remu32(i32 %a, i32 %b) {
define signext i16 @remi16(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: remi16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -75,8 +69,6 @@ define signext i16 @remi16(i16 signext %a, i16 signext %b) {
define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: remu16:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -90,8 +82,6 @@ define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
define signext i8 @remi8(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: remi8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -109,8 +99,6 @@ define signext i8 @remi8(i8 signext %a, i8 signext %b) {
define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: remu8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s2, %s0, %s1
; CHECK-NEXT: muls.w.sx %s1, %s2, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -136,7 +124,6 @@ define i64 @remi64ri(i64 %a, i64 %b) {
define i32 @remi32ri(i32 %a, i32 %b) {
; CHECK-LABEL: remi32ri:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divs.w.sx %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -161,7 +148,6 @@ define i64 @remu64ri(i64 %a, i64 %b) {
define i32 @remu32ri(i32 %a, i32 %b) {
; CHECK-LABEL: remu32ri:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: divu.w %s1, %s0, (62)0
; CHECK-NEXT: muls.w.sx %s1, 3, %s1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
@@ -186,9 +172,8 @@ define i64 @remi64li(i64 %a, i64 %b) {
define i32 @remi32li(i32 %a, i32 %b) {
; CHECK-LABEL: remi32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: divs.w.sx %s1, 3, %s0
-; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
+; CHECK-NEXT: divs.w.sx %s0, 3, %s1
+; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = srem i32 3, %b
@@ -211,9 +196,8 @@ define i64 @remu64li(i64 %a, i64 %b) {
define i32 @remu32li(i32 %a, i32 %b) {
; CHECK-LABEL: remu32li:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT: divu.w %s1, 3, %s0
-; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
+; CHECK-NEXT: divu.w %s0, 3, %s1
+; CHECK-NEXT: muls.w.sx %s0, %s0, %s1
; CHECK-NEXT: subs.w.sx %s0, 3, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = urem i32 3, %b
diff --git a/llvm/test/CodeGen/VE/right_shift.ll b/llvm/test/CodeGen/VE/right_shift.ll
index 87ac6df7e62e..cd8bcf714ffa 100644
--- a/llvm/test/CodeGen/VE/right_shift.ll
+++ b/llvm/test/CodeGen/VE/right_shift.ll
@@ -3,8 +3,6 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
@@ -18,8 +16,6 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
@@ -33,8 +29,6 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = ashr i32 %0, %1
@@ -44,7 +38,6 @@ define i32 @func3(i32 %0, i32 %1) {
define i64 @func4(i64 %0, i64 %1) {
; CHECK-LABEL: func4:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: sra.l %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = ashr i64 %0, %1
@@ -54,8 +47,6 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
@@ -70,8 +61,6 @@ define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
@@ -86,8 +75,6 @@ define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
define i32 @func9(i32 %0, i32 %1) {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
@@ -98,7 +85,6 @@ define i32 @func9(i32 %0, i32 %1) {
define i64 @func10(i64 %0, i64 %1) {
; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: srl %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = lshr i64 %0, %1
@@ -108,7 +94,6 @@ define i64 @func10(i64 %0, i64 %1) {
define signext i8 @func12(i8 signext %0) {
; CHECK-LABEL: func12:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
@@ -119,7 +104,6 @@ define signext i8 @func12(i8 signext %0) {
define signext i16 @func13(i16 signext %0) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
@@ -130,7 +114,6 @@ define signext i16 @func13(i16 signext %0) {
define i32 @func14(i32 %0) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sra.w.sx %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
%2 = ashr i32 %0, 5
@@ -149,7 +132,6 @@ define i64 @func15(i64 %0) {
define zeroext i8 @func17(i8 zeroext %0) {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
@@ -161,7 +143,6 @@ define zeroext i8 @func17(i8 zeroext %0) {
define zeroext i16 @func18(i16 zeroext %0) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
@@ -173,7 +154,6 @@ define zeroext i16 @func18(i16 zeroext %0) {
define i32 @func19(i32 %0) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: srl %s0, %s0, 5
; CHECK-NEXT: or %s11, 0, %s9
diff --git a/llvm/test/CodeGen/VE/rotl.ll b/llvm/test/CodeGen/VE/rotl.ll
index cc5e004478ab..60ae901c64f0 100644
--- a/llvm/test/CodeGen/VE/rotl.ll
+++ b/llvm/test/CodeGen/VE/rotl.ll
@@ -3,7 +3,6 @@
define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: sll %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
@@ -22,8 +21,6 @@ define i64 @func1(i64 %a, i32 %b) {
define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: sla.w.sx %s2, %s0, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1
; CHECK-NEXT: and %s0, %s0, (32)0
diff --git a/llvm/test/CodeGen/VE/rotr.ll b/llvm/test/CodeGen/VE/rotr.ll
index 93dcbbc7e0a8..9f11de7bd8d4 100644
--- a/llvm/test/CodeGen/VE/rotr.ll
+++ b/llvm/test/CodeGen/VE/rotr.ll
@@ -3,7 +3,6 @@
define i64 @func1(i64 %a, i32 %b) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
; CHECK-NEXT: srl %s2, %s0, %s1
; CHECK-NEXT: lea %s3, 64
; CHECK-NEXT: subs.w.sx %s1, %s3, %s1
@@ -22,8 +21,6 @@ define i64 @func1(i64 %a, i32 %b) {
define i32 @func2(i32 %a, i32 %b) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: and %s2, %s0, (32)0
; CHECK-NEXT: srl %s2, %s2, %s1
; CHECK-NEXT: subs.w.sx %s1, 32, %s1
diff --git a/llvm/test/CodeGen/VE/select.ll b/llvm/test/CodeGen/VE/select.ll
index 81234d3d955c..f4b97deea725 100644
--- a/llvm/test/CodeGen/VE/select.ll
+++ b/llvm/test/CodeGen/VE/select.ll
@@ -36,10 +36,8 @@ define i64 @selecti64(i1 zeroext, i64, i64) {
define i32 @selecti32(i1 zeroext, i32, i32) {
; CHECK-LABEL: selecti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s3, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s2, (0)1
-; CHECK-NEXT: cmov.w.ne %s0, %s1, %s3
+; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
+; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: or %s11, 0, %s9
%4 = select i1 %0, i32 %1, i32 %2
ret i32 %4
@@ -48,9 +46,6 @@ define i32 @selecti32(i1 zeroext, i32, i32) {
define zeroext i1 @selecti1(i1 zeroext, i1 zeroext, i1 zeroext) {
; CHECK-LABEL: selecti1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
; CHECK-NEXT: cmov.w.ne %s2, %s1, %s0
; CHECK-NEXT: adds.w.zx %s0, %s2, (0)1
; CHECK-NEXT: or %s11, 0, %s9
diff --git a/llvm/test/CodeGen/VE/selectccf32c.ll b/llvm/test/CodeGen/VE/selectccf32c.ll
index 54a9da4c8e46..aed2cad78a5b 100644
--- a/llvm/test/CodeGen/VE/selectccf32c.ll
+++ b/llvm/test/CodeGen/VE/selectccf32c.ll
@@ -35,8 +35,6 @@ define float @selectccsgti16(i16, i16, float, float) {
define float @selectccsgti32(i32, i32, float, float) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/selectccf64c.ll b/llvm/test/CodeGen/VE/selectccf64c.ll
index 24b61ece8d54..cef221ef87a7 100644
--- a/llvm/test/CodeGen/VE/selectccf64c.ll
+++ b/llvm/test/CodeGen/VE/selectccf64c.ll
@@ -35,8 +35,6 @@ define double @selectccsgti16(i16, i16, double, double) {
define double @selectccsgti32(i32, i32, double, double) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/selectcci32.ll b/llvm/test/CodeGen/VE/selectcci32.ll
index af1861487b89..323ef4df49ee 100644
--- a/llvm/test/CodeGen/VE/selectcci32.ll
+++ b/llvm/test/CodeGen/VE/selectcci32.ll
@@ -3,12 +3,9 @@
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.eq %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp eq i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -18,12 +15,9 @@ define i32 @selectcceq(i32, i32, i32, i32) {
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.ne %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ne i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -33,12 +27,9 @@ define i32 @selectccne(i32, i32, i32, i32) {
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -48,12 +39,9 @@ define i32 @selectccsgt(i32, i32, i32, i32) {
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -63,12 +51,9 @@ define i32 @selectccsge(i32, i32, i32, i32) {
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp slt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -78,12 +63,9 @@ define i32 @selectccslt(i32, i32, i32, i32) {
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sle i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -93,12 +75,9 @@ define i32 @selectccsle(i32, i32, i32, i32) {
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -108,12 +87,9 @@ define i32 @selectccugt(i32, i32, i32, i32) {
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -123,12 +99,9 @@ define i32 @selectccuge(i32, i32, i32, i32) {
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -138,12 +111,9 @@ define i32 @selectccult(i32, i32, i32, i32) {
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -153,12 +123,9 @@ define i32 @selectccule(i32, i32, i32, i32) {
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -168,12 +135,9 @@ define i32 @selectccugt2(i32, i32, i32, i32) {
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -183,12 +147,9 @@ define i32 @selectccuge2(i32, i32, i32, i32) {
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -198,12 +159,9 @@ define i32 @selectccult2(i32, i32, i32, i32) {
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
diff --git a/llvm/test/CodeGen/VE/selectcci32c.ll b/llvm/test/CodeGen/VE/selectcci32c.ll
index e4017c46c579..67878352dec6 100644
--- a/llvm/test/CodeGen/VE/selectcci32c.ll
+++ b/llvm/test/CodeGen/VE/selectcci32c.ll
@@ -6,11 +6,10 @@ define i32 @selectccsgti8(i8, i8, i32, i32) {
; CHECK-NEXT: sll %s1, %s1, 56
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
-; CHECK-NEXT: sra.l %s4, %s0, 56
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: sra.l %s0, %s0, 56
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i8 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -23,11 +22,10 @@ define i32 @selectccsgti16(i16, i16, i32, i32) {
; CHECK-NEXT: sll %s1, %s1, 48
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
-; CHECK-NEXT: sra.l %s4, %s0, 48
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: sra.l %s0, %s0, 48
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i16 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -37,12 +35,9 @@ define i32 @selectccsgti16(i16, i16, i32, i32) {
define i32 @selectccsgti32(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i32 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -52,11 +47,9 @@ define i32 @selectccsgti32(i32, i32, i32, i32) {
define i32 @selectccsgti64(i64, i64, i32, i32) {
; CHECK-LABEL: selectccsgti64:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s4, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s3, (0)1
; CHECK-NEXT: cmps.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s2, %s4, %s0
-; CHECK-NEXT: or %s0, 0, %s2
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i64 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -66,19 +59,17 @@ define i32 @selectccsgti64(i64, i64, i32, i32) {
define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-LABEL: selectccsgti128:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s6, %s4, (0)1
-; CHECK-NEXT: adds.w.sx %s4, %s5, (0)1
-; CHECK-NEXT: or %s5, 0, (0)1
+; CHECK-NEXT: or %s6, 0, (0)1
; CHECK-NEXT: cmps.l %s1, %s1, %s3
-; CHECK-NEXT: or %s3, 0, %s5
+; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s5, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s5, %s1
+; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0
-; CHECK-NEXT: cmov.w.ne %s4, %s6, %s0
-; CHECK-NEXT: or %s0, 0, %s4
+; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
+; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i128 %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -88,11 +79,9 @@ define i32 @selectccsgti128(i128, i128, i32, i32) {
define i32 @selectccogtf32(float, float, i32, i32) {
; CHECK-LABEL: selectccogtf32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s4, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s3, (0)1
; CHECK-NEXT: fcmp.s %s0, %s0, %s1
-; CHECK-NEXT: cmov.s.gt %s2, %s4, %s0
-; CHECK-NEXT: or %s0, 0, %s2
+; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = fcmp ogt float %0, %1
%6 = select i1 %5, i32 %2, i32 %3
@@ -102,11 +91,9 @@ define i32 @selectccogtf32(float, float, i32, i32) {
define i32 @selectccogtf64(double, double, i32, i32) {
; CHECK-LABEL: selectccogtf64:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s4, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s3, (0)1
; CHECK-NEXT: fcmp.d %s0, %s0, %s1
-; CHECK-NEXT: cmov.d.gt %s2, %s4, %s0
-; CHECK-NEXT: or %s0, 0, %s2
+; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = fcmp ogt double %0, %1
%6 = select i1 %5, i32 %2, i32 %3
diff --git a/llvm/test/CodeGen/VE/selectcci32i.ll b/llvm/test/CodeGen/VE/selectcci32i.ll
index a4cccd0ebf93..b1fce36d1b0c 100644
--- a/llvm/test/CodeGen/VE/selectcci32i.ll
+++ b/llvm/test/CodeGen/VE/selectcci32i.ll
@@ -3,12 +3,10 @@
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.eq %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp eq i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -18,12 +16,10 @@ define i32 @selectcceq(i32, i32, i32, i32) {
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.ne %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ne i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -33,12 +29,10 @@ define i32 @selectccne(i32, i32, i32, i32) {
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sgt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -48,12 +42,10 @@ define i32 @selectccsgt(i32, i32, i32, i32) {
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 11, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 11, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -63,12 +55,10 @@ define i32 @selectccsge(i32, i32, i32, i32) {
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp slt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -78,12 +68,10 @@ define i32 @selectccslt(i32, i32, i32, i32) {
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 13, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 13, (0)1
+; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp sle i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -93,12 +81,10 @@ define i32 @selectccsle(i32, i32, i32, i32) {
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -108,12 +94,10 @@ define i32 @selectccugt(i32, i32, i32, i32) {
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 11, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 11, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -123,12 +107,10 @@ define i32 @selectccuge(i32, i32, i32, i32) {
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -138,12 +120,10 @@ define i32 @selectccult(i32, i32, i32, i32) {
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 13, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 13, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -153,12 +133,10 @@ define i32 @selectccule(i32, i32, i32, i32) {
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ugt i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -168,12 +146,10 @@ define i32 @selectccugt2(i32, i32, i32, i32) {
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 11, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 11, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp uge i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -183,12 +159,10 @@ define i32 @selectccuge2(i32, i32, i32, i32) {
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 12, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 12, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ult i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
@@ -198,12 +172,10 @@ define i32 @selectccult2(i32, i32, i32, i32) {
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT: adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT: or %s3, 13, (0)1
-; CHECK-NEXT: cmpu.w %s1, %s1, %s3
-; CHECK-NEXT: cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT: or %s1, 13, (0)1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: or %s11, 0, %s9
%5 = icmp ule i32 %0, 12
%6 = select i1 %5, i32 %2, i32 %3
diff --git a/llvm/test/CodeGen/VE/selectcci64c.ll b/llvm/test/CodeGen/VE/selectcci64c.ll
index 276f23d9a5ff..75c54f6ad97c 100644
--- a/llvm/test/CodeGen/VE/selectcci64c.ll
+++ b/llvm/test/CodeGen/VE/selectcci64c.ll
@@ -35,8 +35,6 @@ define i64 @selectccsgti16(i16, i16, i64, i64) {
define i64 @selectccsgti32(i32, i32, i64, i64) {
; CHECK-LABEL: selectccsgti32:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
diff --git a/llvm/test/CodeGen/VE/setcci32.ll b/llvm/test/CodeGen/VE/setcci32.ll
index 15bf130fec8b..f13db8093183 100644
--- a/llvm/test/CodeGen/VE/setcci32.ll
+++ b/llvm/test/CodeGen/VE/setcci32.ll
@@ -3,8 +3,6 @@
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
@@ -17,8 +15,6 @@ define zeroext i1 @setcceq(i32, i32) {
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
@@ -31,8 +27,6 @@ define zeroext i1 @setccne(i32, i32) {
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
@@ -45,8 +39,6 @@ define zeroext i1 @setccugt(i32, i32) {
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
@@ -59,8 +51,6 @@ define zeroext i1 @setccuge(i32, i32) {
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
@@ -73,8 +63,6 @@ define zeroext i1 @setccult(i32, i32) {
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
@@ -87,8 +75,6 @@ define zeroext i1 @setccule(i32, i32) {
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s1, (63)0, %s0
@@ -101,8 +87,6 @@ define zeroext i1 @setccsgt(i32, i32) {
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s1, (63)0, %s0
@@ -115,8 +99,6 @@ define zeroext i1 @setccsge(i32, i32) {
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s1, (63)0, %s0
@@ -129,8 +111,6 @@ define zeroext i1 @setccslt(i32, i32) {
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: cmov.w.le %s1, (63)0, %s0
diff --git a/llvm/test/CodeGen/VE/setcci32i.ll b/llvm/test/CodeGen/VE/setcci32i.ll
index ac226190ae44..57152799f3c7 100644
--- a/llvm/test/CodeGen/VE/setcci32i.ll
+++ b/llvm/test/CodeGen/VE/setcci32i.ll
@@ -3,7 +3,6 @@
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -17,7 +16,6 @@ define zeroext i1 @setcceq(i32, i32) {
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -31,7 +29,6 @@ define zeroext i1 @setccne(i32, i32) {
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -45,7 +42,6 @@ define zeroext i1 @setccugt(i32, i32) {
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -59,7 +55,6 @@ define zeroext i1 @setccuge(i32, i32) {
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -73,7 +68,6 @@ define zeroext i1 @setccult(i32, i32) {
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -87,7 +81,6 @@ define zeroext i1 @setccule(i32, i32) {
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -101,7 +94,6 @@ define zeroext i1 @setccsgt(i32, i32) {
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -115,7 +107,6 @@ define zeroext i1 @setccsge(i32, i32) {
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
@@ -129,7 +120,6 @@ define zeroext i1 @setccslt(i32, i32) {
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
diff --git a/llvm/test/CodeGen/VE/subtraction.ll b/llvm/test/CodeGen/VE/subtraction.ll
index 43a30bfe1e1b..c3c6beeceda5 100644
--- a/llvm/test/CodeGen/VE/subtraction.ll
+++ b/llvm/test/CodeGen/VE/subtraction.ll
@@ -3,8 +3,6 @@
define signext i8 @func1(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -16,8 +14,6 @@ define signext i8 @func1(i8 signext %0, i8 signext %1) {
define signext i16 @func2(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -29,8 +25,6 @@ define signext i16 @func2(i16 signext %0, i16 signext %1) {
define i32 @func3(i32 %0, i32 %1) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub nsw i32 %0, %1
@@ -49,8 +43,6 @@ define i64 @func4(i64 %0, i64 %1) {
define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -61,8 +53,6 @@ define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -73,8 +63,6 @@ define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
define i32 @func8(i32 %0, i32 %1) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: subs.w.sx %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%3 = sub i32 %0, %1
@@ -93,7 +81,6 @@ define i64 @func9(i64 %0, i64 %1) {
define signext i8 @func13(i8 signext %0, i8 signext %1) {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
@@ -105,7 +92,6 @@ define signext i8 @func13(i8 signext %0, i8 signext %1) {
define signext i16 @func14(i16 signext %0, i16 signext %1) {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
@@ -117,7 +103,6 @@ define signext i16 @func14(i16 signext %0, i16 signext %1) {
define i32 @func15(i32 %0, i32 %1) {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add nsw i32 %0, -5
@@ -136,7 +121,6 @@ define i64 @func16(i64 %0, i64 %1) {
define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (56)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -147,7 +131,6 @@ define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) {
define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) {
; CHECK-LABEL: func19:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
@@ -158,7 +141,6 @@ define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) {
define i32 @func20(i32 %0, i32 %1) {
; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s0, -5, %s0
; CHECK-NEXT: or %s11, 0, %s9
%3 = add i32 %0, -5
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