[PATCH] D85456: Fix instruction counting in post-RA scheduler

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: arsenm, kerbowa.
Herald added subscribers: javed.absar, hiraditya, nhaehnle, jvesely.
Herald added a project: LLVM.
rampitec requested review of this revision.
Herald added a subscriber: wdng.

That is possible to bundle instructions but have no leading
BUNDLE. In such a case post-RA scheduler miscalculates a number
of instructions and asserts. The bundle in the test was created
by the Greedy.


https://reviews.llvm.org/D85456

Files:
  llvm/lib/CodeGen/PostRASchedulerList.cpp
  llvm/test/CodeGen/AMDGPU/bundled_insts_no_bundle.mir


Index: llvm/test/CodeGen/AMDGPU/bundled_insts_no_bundle.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/bundled_insts_no_bundle.mir
@@ -0,0 +1,18 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+---
+# GCN-LABEL: name: bundled_insts_no_bundle
+# GCN:      entry:
+# GCN-NEXT:   $sgpr0 = KILL undef $sgpr0 {
+# GCN-NEXT:     $sgpr1 = KILL undef $sgpr1
+# GCN-NEXT:   }
+
+name: bundled_insts_no_bundle
+body:             |
+  bb.0.entry:
+
+    $sgpr0 = KILL undef $sgpr0 {
+      $sgpr1 = KILL undef $sgpr1
+    }
+
+...
Index: llvm/lib/CodeGen/PostRASchedulerList.cpp
===================================================================
--- llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -349,7 +349,7 @@
         Scheduler.Observe(MI, CurrentCount);
       }
       I = MI;
-      if (MI.isBundle())
+      if (MI.isBundledWithSucc())
         Count -= MI.getBundleSize();
     }
     assert(Count == 0 && "Instruction count mismatch!");


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