[PATCH] D85479: [SVE][VLS] Don't combine logical AND.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
fpetrogalli added reviewers: paulwalker-arm, cameron.mcinally, david-arm.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.
fpetrogalli requested review of this revision.

Testing is performed when targeting 128, 256 and 512-bit wide vectors.

For 128-bit vectors, the original behavior of using NEON instructions is
preserved.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85479

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vls-sve-128-and.ll
  llvm/test/CodeGen/AArch64/vls-sve-256-and.ll
  llvm/test/CodeGen/AArch64/vls-sve-512-and.ll

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