[PATCH] D85364: [SVE][WIP] Implement lowering for fixed width select

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Just to better put my position in words.  This patch does highlight the expected problem with the fixed length code generation for SVE approach, namely extensions and truncations are more costly than they need to be for SVE.  At the block level my expectation is that most should get folded away as more and more of the fixed length operations are lowered to SVE.  Here though is where my expectation does not match reality because I believe we lower the ext/trunc operations too early meaning we don't have a DAGCombine phase that's able to remove them.  This is why my original prototype made these operations legal and effectively lowered them during selection.  That said it's presumably possible to recognise the target equivalent patterns?

This will not help when crossing block boundaries (perhaps it will for global isel?) so ultimately for the best code quality[1] we're going to want to consider i1 based vectors legal but that is not a straight forward transformation (perhaps a topic for the SVE sync call?) and while "expanding"  operations is a much bigger performance issue I'd rather remained focused on that.  Of course there's the argument that the more we move along the current path the harder it will be to change, but currently there's only a handful of functions that relate to this and I'm continually monitoring it.

[1] Well, other than using scalable vectors directly :)


Repository:
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  https://reviews.llvm.org/D85364/new/

https://reviews.llvm.org/D85364