[llvm] 90eb7d5 - AMDGPU: Fix spilling of 96-bit AGPRs
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 6 09:52:06 PDT 2020
Author: Matt Arsenault
Date: 2020-08-06T12:42:07-04:00
New Revision: 90eb7d5283df7655188142d8e0c064bd4a688e00
URL: https://github.com/llvm/llvm-project/commit/90eb7d5283df7655188142d8e0c064bd4a688e00
DIFF: https://github.com/llvm/llvm-project/commit/90eb7d5283df7655188142d8e0c064bd4a688e00.diff
LOG: AMDGPU: Fix spilling of 96-bit AGPRs
Added:
Modified:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/test/CodeGen/AMDGPU/spill-agpr.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ef5ed59f6a45..52fa3880a7f5 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1277,6 +1277,8 @@ static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
return AMDGPU::SI_SPILL_A32_SAVE;
case 8:
return AMDGPU::SI_SPILL_A64_SAVE;
+ case 12:
+ return AMDGPU::SI_SPILL_A96_SAVE;
case 16:
return AMDGPU::SI_SPILL_A128_SAVE;
case 64:
@@ -1406,6 +1408,8 @@ static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
return AMDGPU::SI_SPILL_A32_RESTORE;
case 8:
return AMDGPU::SI_SPILL_A64_RESTORE;
+ case 12:
+ return AMDGPU::SI_SPILL_A96_RESTORE;
case 16:
return AMDGPU::SI_SPILL_A128_RESTORE;
case 64:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 3b3f725fe172..f3ae14860be9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -716,6 +716,7 @@ defm SI_SPILL_V1024 : SI_SPILL_VGPR <VReg_1024>;
defm SI_SPILL_A32 : SI_SPILL_VGPR <AGPR_32, 1>;
defm SI_SPILL_A64 : SI_SPILL_VGPR <AReg_64, 1>;
+defm SI_SPILL_A96 : SI_SPILL_VGPR <AReg_96, 1>;
defm SI_SPILL_A128 : SI_SPILL_VGPR <AReg_128, 1>;
defm SI_SPILL_A512 : SI_SPILL_VGPR <AReg_512, 1>;
defm SI_SPILL_A1024 : SI_SPILL_VGPR <AReg_1024, 1>;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 6db8ad9b6d02..34609cf02928 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -577,6 +577,8 @@ static unsigned getNumSubRegsForSpillOp(unsigned Op) {
case AMDGPU::SI_SPILL_S96_RESTORE:
case AMDGPU::SI_SPILL_V96_SAVE:
case AMDGPU::SI_SPILL_V96_RESTORE:
+ case AMDGPU::SI_SPILL_A96_SAVE:
+ case AMDGPU::SI_SPILL_A96_RESTORE:
return 3;
case AMDGPU::SI_SPILL_S64_SAVE:
case AMDGPU::SI_SPILL_S64_RESTORE:
@@ -1277,6 +1279,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_A1024_SAVE:
case AMDGPU::SI_SPILL_A512_SAVE:
case AMDGPU::SI_SPILL_A128_SAVE:
+ case AMDGPU::SI_SPILL_A96_SAVE:
case AMDGPU::SI_SPILL_A64_SAVE:
case AMDGPU::SI_SPILL_A32_SAVE: {
const MachineOperand *VData = TII->getNamedOperand(*MI,
@@ -1306,6 +1309,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
case AMDGPU::SI_SPILL_V1024_RESTORE:
case AMDGPU::SI_SPILL_A32_RESTORE:
case AMDGPU::SI_SPILL_A64_RESTORE:
+ case AMDGPU::SI_SPILL_A96_RESTORE:
case AMDGPU::SI_SPILL_A128_RESTORE:
case AMDGPU::SI_SPILL_A512_RESTORE:
case AMDGPU::SI_SPILL_A1024_RESTORE: {
diff --git a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir
index 3ce09c795ef3..b40aa91cbbf2 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-agpr.mir
+++ b/llvm/test/CodeGen/AMDGPU/spill-agpr.mir
@@ -195,3 +195,52 @@ body: |
S_NOP 0, implicit undef $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255
S_NOP 0, implicit %0
...
+
+---
+name: spill_restore_agpr96
+tracksRegLiveness: true
+machineFunctionInfo:
+ scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
+ stackPtrOffsetReg: $sgpr32
+body: |
+ ; SPILLED-LABEL: name: spill_restore_agpr96
+ ; SPILLED: bb.0:
+ ; SPILLED: successors: %bb.1(0x80000000)
+ ; SPILLED: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2
+ ; SPILLED: SI_SPILL_A96_SAVE killed $agpr0_agpr1_agpr2, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 12 into %stack.0, align 4, addrspace 5)
+ ; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+ ; SPILLED: bb.1:
+ ; SPILLED: successors: %bb.2(0x80000000)
+ ; SPILLED: S_NOP 1
+ ; SPILLED: bb.2:
+ ; SPILLED: $agpr0_agpr1_agpr2 = SI_SPILL_A96_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 12 from %stack.0, align 4, addrspace 5)
+ ; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2
+ ; EXPANDED-LABEL: name: spill_restore_agpr96
+ ; EXPANDED: bb.0:
+ ; EXPANDED: successors: %bb.1(0x80000000)
+ ; EXPANDED: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; EXPANDED: S_NOP 0, implicit-def renamable $agpr0_agpr1_agpr2
+ ; EXPANDED: $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec, implicit $agpr0_agpr1_agpr2
+ ; EXPANDED: $vgpr1 = V_ACCVGPR_READ_B32 killed $agpr1, implicit $exec, implicit $agpr0_agpr1_agpr2
+ ; EXPANDED: $vgpr2 = V_ACCVGPR_READ_B32 killed $agpr2, implicit $exec, implicit killed $agpr0_agpr1_agpr2
+ ; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+ ; EXPANDED: bb.1:
+ ; EXPANDED: successors: %bb.2(0x80000000)
+ ; EXPANDED: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; EXPANDED: S_NOP 1
+ ; EXPANDED: bb.2:
+ ; EXPANDED: liveins: $vgpr0, $vgpr1, $vgpr2
+ ; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; EXPANDED: $agpr1 = V_ACCVGPR_WRITE_B32 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; EXPANDED: $agpr2 = V_ACCVGPR_WRITE_B32 $vgpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2
+ ; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2
+ bb.0:
+ S_NOP 0, implicit-def %0:areg_96
+ S_CBRANCH_SCC1 implicit undef $scc, %bb.1
+
+ bb.1:
+ S_NOP 1
+
+ bb.2:
+ S_NOP 0, implicit %0
+...
More information about the llvm-commits
mailing list