[llvm] 56270d1 - AMDGPU/GlobalISel: Start trying to handle AGPR bank
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 6 09:39:58 PDT 2020
Author: Matt Arsenault
Date: 2020-08-06T12:39:50-04:00
New Revision: 56270d1d421e00c98be169d9734c84350660781c
URL: https://github.com/llvm/llvm-project/commit/56270d1d421e00c98be169d9734c84350660781c
DIFF: https://github.com/llvm/llvm-project/commit/56270d1d421e00c98be169d9734c84350660781c.diff
LOG: AMDGPU/GlobalISel: Start trying to handle AGPR bank
Try to use AGPR banks for the various merge/unmerge type
operations. Previously these would introduce copies to VGPR.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 7e664492ee46..ac800eac9d0e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3106,6 +3106,59 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
return applyDefaultMapping(OpdMapper);
}
+// vgpr, sgpr -> vgpr
+// vgpr, agpr -> vgpr
+// agpr, agpr -> agpr
+// agpr, sgpr -> vgpr
+static unsigned regBankUnion(unsigned RB0, unsigned RB1) {
+ if (RB0 == AMDGPU::InvalidRegBankID)
+ return RB1;
+ if (RB1 == AMDGPU::InvalidRegBankID)
+ return RB0;
+
+ if (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID)
+ return AMDGPU::SGPRRegBankID;
+
+ if (RB0 == AMDGPU::AGPRRegBankID && RB1 == AMDGPU::AGPRRegBankID)
+ return AMDGPU::AGPRRegBankID;
+
+ return AMDGPU::VGPRRegBankID;
+}
+
+static unsigned regBankBoolUnion(unsigned RB0, unsigned RB1) {
+ if (RB0 == AMDGPU::InvalidRegBankID)
+ return RB1;
+ if (RB1 == AMDGPU::InvalidRegBankID)
+ return RB0;
+
+ // vcc, vcc -> vcc
+ // vcc, sgpr -> vcc
+ // vcc, vgpr -> vcc
+ if (RB0 == AMDGPU::VCCRegBankID || RB1 == AMDGPU::VCCRegBankID)
+ return AMDGPU::VCCRegBankID;
+
+ // vcc, vgpr -> vgpr
+ return regBankUnion(RB0, RB1);
+}
+
+unsigned AMDGPURegisterBankInfo::getMappingType(const MachineRegisterInfo &MRI,
+ const MachineInstr &MI) const {
+ unsigned RegBank = AMDGPU::InvalidRegBankID;
+
+ for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
+ if (!MI.getOperand(i).isReg())
+ continue;
+ Register Reg = MI.getOperand(i).getReg();
+ if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) {
+ RegBank = regBankUnion(RegBank, Bank->getID());
+ if (RegBank == AMDGPU::VGPRRegBankID)
+ break;
+ }
+ }
+
+ return RegBank;
+}
+
bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
@@ -3296,28 +3349,6 @@ AMDGPURegisterBankInfo::getRegBankID(Register Reg,
return Bank ? Bank->getID() : Default;
}
-
-static unsigned regBankUnion(unsigned RB0, unsigned RB1) {
- return (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) ?
- AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
-}
-
-static unsigned regBankBoolUnion(unsigned RB0, unsigned RB1) {
- if (RB0 == AMDGPU::InvalidRegBankID)
- return RB1;
- if (RB1 == AMDGPU::InvalidRegBankID)
- return RB0;
-
- // vcc, vcc -> vcc
- // vcc, sgpr -> vcc
- // vcc, vgpr -> vcc
- if (RB0 == AMDGPU::VCCRegBankID || RB1 == AMDGPU::VCCRegBankID)
- return AMDGPU::VCCRegBankID;
-
- // vcc, vgpr -> vgpr
- return regBankUnion(RB0, RB1);
-}
-
const RegisterBankInfo::ValueMapping *
AMDGPURegisterBankInfo::getSGPROpMapping(Register Reg,
const MachineRegisterInfo &MRI,
@@ -3618,8 +3649,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
case AMDGPU::G_INSERT: {
- unsigned BankID = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
- AMDGPU::VGPRRegBankID;
+ unsigned BankID = getMappingType(MRI, MI);
unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
@@ -3658,8 +3688,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
case AMDGPU::G_MERGE_VALUES:
case AMDGPU::G_CONCAT_VECTORS: {
- unsigned Bank = isSALUMapping(MI) ?
- AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
+ unsigned Bank = getMappingType(MRI, MI);
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
@@ -3826,8 +3855,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
case AMDGPU::G_UNMERGE_VALUES: {
- unsigned Bank = isSALUMapping(MI) ? AMDGPU::SGPRRegBankID :
- AMDGPU::VGPRRegBankID;
+ unsigned Bank = getMappingType(MRI, MI);
// Op1 and Dst should use the same register bank.
// FIXME: Shouldn't this be the default? Why do we need to handle this?
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
index 2cfb32201a6a..59a60aad96e7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
@@ -149,6 +149,9 @@ class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo {
getInstrAlternativeMappingsIntrinsicWSideEffects(
const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
+ unsigned getMappingType(const MachineRegisterInfo &MRI,
+ const MachineInstr &MI) const;
+
bool isSALUMapping(const MachineInstr &MI) const;
const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
index 3ec16a7b1314..20e0ee62a37b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: build_vector_v2s32_ss
@@ -67,3 +67,114 @@ body: |
%1:_(s32) = COPY $vgpr1
%2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
...
+
+---
+name: build_vector_v2s32_aa
+tracksRegLiveness: true
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $agpr1
+
+ ; CHECK-LABEL: name: build_vector_v2s32_aa
+ ; CHECK: liveins: $agpr0, $agpr1
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:agpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $agpr1
+ %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: build_vector_v2s32_va
+tracksRegLiveness: true
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $agpr0
+
+ ; CHECK-LABEL: name: build_vector_v2s32_va
+ ; CHECK: liveins: $vgpr0, $agpr0
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY2]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $agpr0
+ %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: build_vector_v2s32_av
+tracksRegLiveness: true
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $agpr0
+
+ ; CHECK-LABEL: name: build_vector_v2s32_av
+ ; CHECK: liveins: $vgpr0, $agpr0
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $vgpr0
+ %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: build_vector_v2s32_sa
+tracksRegLiveness: true
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $agpr0
+
+ ; CHECK-LABEL: name: build_vector_v2s32_sa
+ ; CHECK: liveins: $sgpr0, $agpr0
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $agpr0
+ %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: build_vector_v2s32_as
+tracksRegLiveness: true
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $agpr0
+
+ ; CHECK-LABEL: name: build_vector_v2s32_as
+ ; CHECK: liveins: $sgpr0, $agpr0
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s32>)
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1
+ S_ENDPGM 0, implicit %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
index 01a545b75517..02859c8b25aa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
---
name: concat_vectors_v4s16_ss
@@ -67,3 +67,99 @@ body: |
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
...
+
+---
+name: concat_vectors_v4s16_aa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $agpr1
+ ; CHECK-LABEL: name: concat_vectors_v4s16_aa
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(<2 x s16>) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(<2 x s16>) = COPY $agpr1
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:agpr(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY1]](<2 x s16>)
+ ; CHECK: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
+ %0:_(<2 x s16>) = COPY $agpr0
+ %1:_(<2 x s16>) = COPY $agpr1
+ %2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: concat_vectors_v4s16_av
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $vgpr0
+ ; CHECK-LABEL: name: concat_vectors_v4s16_av
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(<2 x s16>) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[COPY2]](<2 x s16>), [[COPY1]](<2 x s16>)
+ ; CHECK: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
+ %0:_(<2 x s16>) = COPY $agpr0
+ %1:_(<2 x s16>) = COPY $vgpr0
+ %2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: concat_vectors_v4s16_va
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $vgpr0
+ ; CHECK-LABEL: name: concat_vectors_v4s16_va
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(<2 x s16>) = COPY $agpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[COPY]](<2 x s16>), [[COPY2]](<2 x s16>)
+ ; CHECK: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
+ %0:_(<2 x s16>) = COPY $vgpr0
+ %1:_(<2 x s16>) = COPY $agpr0
+ %2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: concat_vectors_v4s16_as
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $sgpr0
+ ; CHECK-LABEL: name: concat_vectors_v4s16_as
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(<2 x s16>) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)
+ ; CHECK: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
+ %0:_(<2 x s16>) = COPY $agpr0
+ %1:_(<2 x s16>) = COPY $sgpr0
+ %2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: concat_vectors_v4s16_sa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $sgpr0
+ ; CHECK-LABEL: name: concat_vectors_v4s16_sa
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(<2 x s16>) = COPY $agpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
+ ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:vgpr(<4 x s16>) = G_CONCAT_VECTORS [[COPY2]](<2 x s16>), [[COPY3]](<2 x s16>)
+ ; CHECK: S_ENDPGM 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
+ %0:_(<2 x s16>) = COPY $sgpr0
+ %1:_(<2 x s16>) = COPY $agpr0
+ %2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
+ S_ENDPGM 0, implicit %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
index 206c9fd2d223..638fa987e48a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: extract_lo32_i64_s
@@ -57,3 +57,19 @@ body: |
%0:_(s1024) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
%1:_(s32) = G_EXTRACT %0, 0
...
+
+---
+name: extract_lo32_i64_a
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1
+ ; CHECK-LABEL: name: extract_lo32_i64_a
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK: [[EXTRACT:%[0-9]+]]:agpr(s32) = G_EXTRACT [[COPY]](s64), 0
+ ; CHECK: S_ENDPGM 0, implicit [[EXTRACT]](s32)
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = G_EXTRACT %0, 0
+ S_ENDPGM 0, implicit %1
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
index e97a6c3ba5e6..4a37d553e4be 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: insert_lo32_i64_ss
@@ -81,3 +81,87 @@ body: |
%1:_(s32) = COPY $vgpr3
%2:_(s96) = G_INSERT %0, %1, 0
...
+
+---
+name: insert_lo32_i64_aa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1, $agpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_aa
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
+ ; CHECK: [[INSERT:%[0-9]+]]:agpr(s64) = G_INSERT [[COPY]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = COPY $agpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_av
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1, $vgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_av
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY1]](s32), 0
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = COPY $vgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_va
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $agpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_va
+ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY]], [[COPY2]](s32), 0
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s32) = COPY $agpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+
+---
+name: insert_lo32_i64_as
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1, $sgpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_as
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32) = COPY $sgpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
+---
+name: insert_lo32_i64_sa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $agpr2
+ ; CHECK-LABEL: name: insert_lo32_i64_sa
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr2
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[INSERT:%[0-9]+]]:vgpr(s64) = G_INSERT [[COPY2]], [[COPY3]](s32), 0
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s32) = COPY $agpr2
+ %2:_(s64) = G_INSERT %0, %1, 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
index 7d1f5d7ff1fc..49bc2b70f118 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
@@ -1,15 +1,15 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
-name: merge_s32_s32_s64_s
+name: merge_s64_s32_s32_ss
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
- ; CHECK-LABEL: name: merge_s32_s32_s64_s
+ ; CHECK-LABEL: name: merge_s64_s32_s32_ss
; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 32
@@ -23,13 +23,13 @@ body: |
...
---
-name: merge_s32_s32_s64_v
+name: merge_s64_s32_s32_s64
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: merge_s32_s32_s64_v
+ ; CHECK-LABEL: name: merge_s64_s32_s32_s64
; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK: [[EXTRACT1:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 32
@@ -42,3 +42,60 @@ body: |
S_ENDPGM 0, implicit %3
...
+---
+name: merge_s64_s32_s32_aa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0, $agpr1
+ ; CHECK-LABEL: name: merge_s64_s32_s32_aa
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
+ ; CHECK: [[MV:%[0-9]+]]:agpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $agpr1
+ %2:_(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: merge_s64_s32_s32_sa
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $agpr0
+ ; CHECK-LABEL: name: merge_s64_s32_s32_sa
+ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $agpr0
+ %2:_(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: merge_s64_s32_s32_as
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $agpr0
+ ; CHECK-LABEL: name: merge_s64_s32_s32_as
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(s64) = G_MERGE_VALUES %0, %1
+ S_ENDPGM 0, implicit %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
index 18b2bf3ffae6..65cd74073266 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefix=FAST %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefix=GREEDY %s
---
name: phi_s32_ss_sbranch
@@ -2374,3 +2374,367 @@ body: |
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
G_BR %bb.1
...
+
+---
+name: phi_s32_aa_sbranch
+legalized: true
+tracksRegLiveness: true
+
+body: |
+ ; FAST-LABEL: name: phi_s32_aa_sbranch
+ ; FAST: bb.0:
+ ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; FAST: liveins: $agpr0, $agpr1, $sgpr2
+ ; FAST: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; FAST: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.1:
+ ; FAST: successors: %bb.2(0x80000000)
+ ; FAST: [[COPY3:%[0-9]+]]:agpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.2:
+ ; FAST: [[PHI:%[0-9]+]]:agpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; FAST: $agpr0 = COPY [[PHI]](s32)
+ ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
+ ; GREEDY-LABEL: name: phi_s32_aa_sbranch
+ ; GREEDY: bb.0:
+ ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GREEDY: liveins: $agpr0, $agpr1, $sgpr2
+ ; GREEDY: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr1
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.1:
+ ; GREEDY: successors: %bb.2(0x80000000)
+ ; GREEDY: [[COPY3:%[0-9]+]]:agpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.2:
+ ; GREEDY: [[PHI:%[0-9]+]]:agpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; GREEDY: $agpr0 = COPY [[PHI]](s32)
+ ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $agpr0, $agpr1, $sgpr2
+
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $agpr1
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ G_BRCOND %4, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s32) = COPY %1
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
+ $agpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+
+---
+name: phi_s32_av_sbranch
+legalized: true
+tracksRegLiveness: true
+
+body: |
+ ; FAST-LABEL: name: phi_s32_av_sbranch
+ ; FAST: bb.0:
+ ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; FAST: liveins: $agpr0, $vgpr0, $sgpr2
+ ; FAST: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.1:
+ ; FAST: successors: %bb.2(0x80000000)
+ ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.2:
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; FAST: $agpr0 = COPY [[PHI]](s32)
+ ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
+ ; GREEDY-LABEL: name: phi_s32_av_sbranch
+ ; GREEDY: bb.0:
+ ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GREEDY: liveins: $agpr0, $vgpr0, $sgpr2
+ ; GREEDY: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.1:
+ ; GREEDY: successors: %bb.2(0x80000000)
+ ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.2:
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; GREEDY: $agpr0 = COPY [[PHI]](s32)
+ ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $agpr0, $vgpr0, $sgpr2
+
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $vgpr0
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ G_BRCOND %4, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s32) = COPY %1
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
+ $agpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+---
+name: phi_s32_va_sbranch
+legalized: true
+tracksRegLiveness: true
+
+body: |
+ ; FAST-LABEL: name: phi_s32_va_sbranch
+ ; FAST: bb.0:
+ ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; FAST: liveins: $agpr0, $vgpr0, $sgpr2
+ ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.1:
+ ; FAST: successors: %bb.2(0x80000000)
+ ; FAST: [[COPY3:%[0-9]+]]:agpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.2:
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; FAST: $agpr0 = COPY [[PHI]](s32)
+ ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
+ ; GREEDY-LABEL: name: phi_s32_va_sbranch
+ ; GREEDY: bb.0:
+ ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GREEDY: liveins: $agpr0, $vgpr0, $sgpr2
+ ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.1:
+ ; GREEDY: successors: %bb.2(0x80000000)
+ ; GREEDY: [[COPY3:%[0-9]+]]:agpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.2:
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; GREEDY: $agpr0 = COPY [[PHI]](s32)
+ ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $agpr0, $vgpr0, $sgpr2
+
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = COPY $agpr0
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ G_BRCOND %4, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s32) = COPY %1
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
+ $agpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+
+---
+name: phi_s32_as_sbranch
+legalized: true
+tracksRegLiveness: true
+
+body: |
+ ; FAST-LABEL: name: phi_s32_as_sbranch
+ ; FAST: bb.0:
+ ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; FAST: liveins: $agpr0, $sgpr0, $sgpr2
+ ; FAST: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.1:
+ ; FAST: successors: %bb.2(0x80000000)
+ ; FAST: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.2:
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; FAST: $agpr0 = COPY [[PHI]](s32)
+ ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
+ ; GREEDY-LABEL: name: phi_s32_as_sbranch
+ ; GREEDY: bb.0:
+ ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GREEDY: liveins: $agpr0, $sgpr0, $sgpr2
+ ; GREEDY: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.1:
+ ; GREEDY: successors: %bb.2(0x80000000)
+ ; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.2:
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; GREEDY: $agpr0 = COPY [[PHI]](s32)
+ ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $agpr0, $sgpr0, $sgpr2
+
+ %0:_(s32) = COPY $agpr0
+ %1:_(s32) = COPY $sgpr0
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ G_BRCOND %4, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s32) = COPY %1
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
+ $agpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
+
+---
+name: phi_s32_sa_sbranch
+legalized: true
+tracksRegLiveness: true
+
+body: |
+ ; FAST-LABEL: name: phi_s32_sa_sbranch
+ ; FAST: bb.0:
+ ; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; FAST: liveins: $agpr0, $sgpr0, $sgpr2
+ ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FAST: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.1:
+ ; FAST: successors: %bb.2(0x80000000)
+ ; FAST: [[COPY3:%[0-9]+]]:agpr(s32) = COPY [[COPY1]](s32)
+ ; FAST: G_BR %bb.2
+ ; FAST: bb.2:
+ ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; FAST: $agpr0 = COPY [[PHI]](s32)
+ ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
+ ; GREEDY-LABEL: name: phi_s32_sa_sbranch
+ ; GREEDY: bb.0:
+ ; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; GREEDY: liveins: $agpr0, $sgpr0, $sgpr2
+ ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GREEDY: [[COPY1:%[0-9]+]]:agpr(s32) = COPY $agpr0
+ ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
+ ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+ ; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
+ ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
+ ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
+ ; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.1:
+ ; GREEDY: successors: %bb.2(0x80000000)
+ ; GREEDY: [[COPY3:%[0-9]+]]:agpr(s32) = COPY [[COPY1]](s32)
+ ; GREEDY: G_BR %bb.2
+ ; GREEDY: bb.2:
+ ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; GREEDY: $agpr0 = COPY [[PHI]](s32)
+ ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $agpr0, $sgpr0, $sgpr2
+
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s32) = COPY $agpr0
+ %2:_(s32) = COPY $sgpr2
+ %3:_(s32) = G_CONSTANT i32 0
+ %4:_(s1) = G_ICMP intpred(eq), %2, %3
+ G_BRCOND %4, %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ successors: %bb.2
+
+ %5:_(s32) = COPY %1
+ G_BR %bb.2
+
+ bb.2:
+ %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
+ $agpr0 = COPY %6
+ S_SETPC_B64 undef $sgpr30_sgpr31
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
index 5a3057224cf3..8ef54c5d9aea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
---
name: test_unmerge_s64_s32_s
@@ -36,3 +36,21 @@ body: |
$vgpr0 = COPY %1(s32)
$vgpr2 = COPY %1(s32)
...
+
+---
+name: test_unmerge_s32_s64_a
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $agpr0_agpr1
+ ; CHECK-LABEL: name: test_unmerge_s32_s64_a
+ ; CHECK: [[COPY:%[0-9]+]]:agpr(s64) = COPY $agpr0_agpr1
+ ; CHECK: [[UV:%[0-9]+]]:agpr(s32), [[UV1:%[0-9]+]]:agpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+ ; CHECK: $agpr0 = COPY [[UV]](s32)
+ ; CHECK: $agpr2 = COPY [[UV1]](s32)
+ %0:_(s64) = COPY $agpr0_agpr1
+ %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0:_(s64)
+ $agpr0 = COPY %1
+ $agpr2 = COPY %2
+...
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