[PATCH] D85441: [SVE][CodeGen] Fix bug with store of unpacked FP scalable vectors
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 6 09:01:57 PDT 2020
david-arm created this revision.
david-arm added reviewers: sdesmalen, efriedma, kmclaughlin.
Herald added subscribers: llvm-commits, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.
david-arm requested review of this revision.
Fixed an incorrect pattern in lib/Target/AArch64/AArch64SVEInstrInfo.td
for storing out <vscale x 2 x f32> unpacked scalable vectors. Added
a couple of tests to
test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D85441
Files:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
Index: llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
+++ llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
@@ -104,3 +104,32 @@
store <vscale x 2 x i64> %data, <vscale x 2 x i64>* %base
ret void
}
+
+
+; Splat stores of unpacked FP scalable vectors
+
+define void @store_nxv2f32(<vscale x 2 x float>* %out) {
+; CHECK-LABEL: store_nxv2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov z0.s, #1.00000000
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: st1w { z0.d }, p0, [x0]
+; CHECK-NEXT: ret
+ %ins = insertelement <vscale x 2 x float> undef, float 1.0, i32 0
+ %splat = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
+ store <vscale x 2 x float> %splat, <vscale x 2 x float>* %out
+ ret void
+}
+
+define void @store_nxv4f16(<vscale x 4 x half>* %out) {
+; CHECK-LABEL: store_nxv4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmov z0.h, #1.00000000
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: st1h { z0.s }, p0, [x0]
+; CHECK-NEXT: ret
+ %ins = insertelement <vscale x 4 x half> undef, half 1.0, i32 0
+ %splat = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
+ store <vscale x 4 x half> %splat, <vscale x 4 x half>* %out
+ ret void
+}
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1797,7 +1797,7 @@
defm : unpred_store< store, nxv4f16, ST1H_S_IMM, PTRUE_S>;
defm : unpred_store< store, nxv2f16, ST1H_D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv4f32, ST1W_IMM, PTRUE_S>;
- defm : unpred_store< store, nxv4f32, ST1W_D_IMM, PTRUE_D>;
+ defm : unpred_store< store, nxv2f32, ST1W_D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv2f64, ST1D_IMM, PTRUE_D>;
multiclass unpred_load<PatFrag Load, ValueType Ty, Instruction RegImmInst,
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