[llvm] d188a60 - AMDGPU: Fix code duplication between the selectors
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 6 07:42:23 PDT 2020
Author: Matt Arsenault
Date: 2020-08-06T10:42:15-04:00
New Revision: d188a608bd89f4792215c6d699f5076fb547685c
URL: https://github.com/llvm/llvm-project/commit/d188a608bd89f4792215c6d699f5076fb547685c
DIFF: https://github.com/llvm/llvm-project/commit/d188a608bd89f4792215c6d699f5076fb547685c.diff
LOG: AMDGPU: Fix code duplication between the selectors
Not sure this is the right place for this helper.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 89bcd39cc60c..a5cc8c8fc306 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1133,28 +1133,6 @@ bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
return true;
}
-static unsigned getDSShaderTypeValue(const MachineFunction &MF) {
- switch (MF.getFunction().getCallingConv()) {
- case CallingConv::AMDGPU_PS:
- return 1;
- case CallingConv::AMDGPU_VS:
- return 2;
- case CallingConv::AMDGPU_GS:
- return 3;
- case CallingConv::AMDGPU_HS:
- case CallingConv::AMDGPU_LS:
- case CallingConv::AMDGPU_ES:
- report_fatal_error("ds_ordered_count unsupported for this calling conv");
- case CallingConv::AMDGPU_CS:
- case CallingConv::AMDGPU_KERNEL:
- case CallingConv::C:
- case CallingConv::Fast:
- default:
- // Assume other calling conventions are various compute callable functions
- return 0;
- }
-}
-
bool AMDGPUInstructionSelector::selectDSOrderedIntrinsic(
MachineInstr &MI, Intrinsic::ID IntrID) const {
MachineBasicBlock *MBB = MI.getParent();
@@ -1186,7 +1164,7 @@ bool AMDGPUInstructionSelector::selectDSOrderedIntrinsic(
report_fatal_error("ds_ordered_count: bad index operand");
unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
- unsigned ShaderType = getDSShaderTypeValue(*MF);
+ unsigned ShaderType = SIInstrInfo::getDSShaderTypeValue(*MF);
unsigned Offset0 = OrderedCountIndex << 2;
unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 678882266b07..ec10d61c79b4 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6641,28 +6641,6 @@ static unsigned getBufferOffsetForMMO(SDValue VOffset,
cast<ConstantSDNode>(Offset)->getSExtValue();
}
-static unsigned getDSShaderTypeValue(const MachineFunction &MF) {
- switch (MF.getFunction().getCallingConv()) {
- case CallingConv::AMDGPU_PS:
- return 1;
- case CallingConv::AMDGPU_VS:
- return 2;
- case CallingConv::AMDGPU_GS:
- return 3;
- case CallingConv::AMDGPU_HS:
- case CallingConv::AMDGPU_LS:
- case CallingConv::AMDGPU_ES:
- report_fatal_error("ds_ordered_count unsupported for this calling conv");
- case CallingConv::AMDGPU_CS:
- case CallingConv::AMDGPU_KERNEL:
- case CallingConv::C:
- case CallingConv::Fast:
- default:
- // Assume other calling conventions are various compute callable functions
- return 0;
- }
-}
-
SDValue SITargetLowering::lowerRawBufferAtomicIntrin(SDValue Op,
SelectionDAG &DAG,
unsigned NewOpcode) const {
@@ -6755,7 +6733,8 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
report_fatal_error("ds_ordered_count: wave_done requires wave_release");
unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
- unsigned ShaderType = getDSShaderTypeValue(DAG.getMachineFunction());
+ unsigned ShaderType =
+ SIInstrInfo::getDSShaderTypeValue(DAG.getMachineFunction());
unsigned Offset0 = OrderedCountIndex << 2;
unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
(Instruction << 4);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index fa05eb5a1323..ef5ed59f6a45 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7208,3 +7208,25 @@ unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
return SchedModel.computeInstrLatency(&MI);
}
+
+unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {
+ switch (MF.getFunction().getCallingConv()) {
+ case CallingConv::AMDGPU_PS:
+ return 1;
+ case CallingConv::AMDGPU_VS:
+ return 2;
+ case CallingConv::AMDGPU_GS:
+ return 3;
+ case CallingConv::AMDGPU_HS:
+ case CallingConv::AMDGPU_LS:
+ case CallingConv::AMDGPU_ES:
+ report_fatal_error("ds_ordered_count unsupported for this calling conv");
+ case CallingConv::AMDGPU_CS:
+ case CallingConv::AMDGPU_KERNEL:
+ case CallingConv::C:
+ case CallingConv::Fast:
+ default:
+ // Assume other calling conventions are various compute callable functions
+ return 0;
+ }
+}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 53e2ffba0f65..0355014bdf3f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1053,6 +1053,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr &MI,
unsigned *PredCost = nullptr) const override;
+
+ static unsigned getDSShaderTypeValue(const MachineFunction &MF);
};
/// \brief Returns true if a reg:subreg pair P has a TRC class
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