[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 requested changes to this revision.
jrtc27 added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1015
 
-let isCall = 0, isBarrier = 0, isCodeGenOnly = 0, hasSideEffects = 0,
-    mayStore = 0, mayLoad = 0 in
+let isCall = 0, isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
+    isCodeGenOnly = 0, hasSideEffects = 0, mayStore = 0, mayLoad = 0 in
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It's not an indirect branch? The code sequence is identical to PseudoTAIL, just with a non-hard-coded temporary register. Any microarchitecture that does macro-op fusion will recognise this sequence as a PC-relative direct jump.


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  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833