[PATCH] D85327: [SVE] Implement lowering for fixed length vector multiplication.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll:652-670
+; Vector i64 multiplications are not legal for NEON so use SVE when available.
+define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
+; CHECK-LABEL: @mul_v1i64
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
+; CHECK: mul z0.d, [[PG]]/m, z0.d, z1.d
+; CHECK: ret
+  %res = mul <1 x i64> %op1, %op2
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As part of the previous revert I removed the NO_SVE check lines from these tests, which means the global "CHECK-NOT for ptrue" will apply.  So I'm hoping I've got the testing covered.  Please let me know if I've misunderstood and extra tests are required.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85327/new/

https://reviews.llvm.org/D85327