[PATCH] D84644: AMDGPU/GlobalISel: Handle llvm.amdgcn.ds.{fadd|fmin|fmax}

[Madhur Amilkanthwar via Phabricator via llvm-commits]

madhur13490 added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3227
+
+bool AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper,
+                                                      MachineInstr &MI,
----------------
"Helper" can be marked as "const"?


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3234
+  MI.setDesc(ST.getInstrInfo()->get(getDSFPAtomicOpcode(IID)));
+  MI.RemoveOperand(1);
+
----------------
You could probably push this inside loop, run loop from 1 to 5 and skip 2 with a comment. That way it would be readable. If its possible then an uptick loop, please.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
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Why just mesa3d? No implication on hsa?


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