[PATCH] D85327: [SVE] Implement lowering for fixed length vector multiplication.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm updated this revision to Diff 283435.
paulwalker-arm added a comment.

Call me a scaredy cat but I'll take the conservative option :)
I've updated the patch to only affect 64/128-bit vector mul operations when wide vectors are enabled.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85327/new/

https://reviews.llvm.org/D85327

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D85327.283435.patch
Type: text/x-patch
Size: 21527 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200805/2e4a38b4/attachment-0001.bin>