[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1100
+
+    if (Subtarget.isISA3_1()) {
+      setOperationAction(ISD::SRA, MVT::v1i128, Legal);
----------------
amyk wrote:
> No brackets are needed here.
> 
> Also, I think it might make sense to move this block into the previous `hasP9Altivec` condition since in there it has:
> ```
>       setOperationAction(ISD::SHL, MVT::v1i128, Legal);
>       setOperationAction(ISD::SRL, MVT::v1i128, Legal);
> ```
Oops, I made that comment above since I thought you were putting the block inside a `hasP9Altivec` block. Sorry. 

Maybe you can move this condition right underneath the `hasP9Altivec` block that contains the `SHL/SRL` to be closer to those instructions. 



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83338/new/

https://reviews.llvm.org/D83338