[llvm] 3e52667 - AMDGPU: Fix verifier error with undef source producing s_bitset*
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 5 11:42:32 PDT 2020
Author: Matt Arsenault
Date: 2020-08-05T14:42:20-04:00
New Revision: 3e52667433881f42ff95ac6775b1ef1a3edd68cd
URL: https://github.com/llvm/llvm-project/commit/3e52667433881f42ff95ac6775b1ef1a3edd68cd
DIFF: https://github.com/llvm/llvm-project/commit/3e52667433881f42ff95ac6775b1ef1a3edd68cd.diff
LOG: AMDGPU: Fix verifier error with undef source producing s_bitset*
This needs to preserve the undef flag.
Added:
llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
llvm/test/CodeGen/AMDGPU/shrink-insts-undef-reg-verifier-error.ll
Modified:
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/test/CodeGen/AMDGPU/andorbitset.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 9c6833a7dab6..8fd7b1abc804 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -374,12 +374,16 @@ static bool shrinkScalarLogicOp(const GCNSubtarget &ST,
}
if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
+ const bool IsUndef = SrcReg->isUndef();
+ const bool IsKill = SrcReg->isKill();
MI.setDesc(TII->get(Opc));
if (Opc == AMDGPU::S_BITSET0_B32 ||
Opc == AMDGPU::S_BITSET1_B32) {
Src0->ChangeToImmediate(NewImm);
// Remove the immediate and add the tied input.
- MI.getOperand(2).ChangeToRegister(Dest->getReg(), false);
+ MI.getOperand(2).ChangeToRegister(Dest->getReg(), /*IsDef*/ false,
+ /*isImp*/ false, IsKill,
+ /*isDead*/ false, IsUndef);
MI.tieOperands(0, 2);
} else {
SrcImm->setImm(NewImm);
diff --git a/llvm/test/CodeGen/AMDGPU/andorbitset.ll b/llvm/test/CodeGen/AMDGPU/andorbitset.ll
index 95bba7d54382..621ab51a7059 100644
--- a/llvm/test/CodeGen/AMDGPU/andorbitset.ll
+++ b/llvm/test/CodeGen/AMDGPU/andorbitset.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: {{^}}s_clear_msb:
; SI: s_bitset0_b32 s{{[0-9]+}}, 31
@@ -47,3 +47,28 @@ define amdgpu_kernel void @s_set_midbit(i32 addrspace(1)* %out, i32 %in) {
store i32 %x, i32 addrspace(1)* %out
ret void
}
+
+; Make sure there's no verifier error with an undef source.
+; SI-LABEL: {{^}}bitset_verifier_error:
+; SI: s_bitset0_b32 s{{[0-9]+}}, 31
+define void @bitset_verifier_error() local_unnamed_addr #0 {
+bb:
+ %i = call float @llvm.fabs.f32(float undef) #0
+ %i1 = bitcast float %i to i32
+ br label %bb2
+
+bb2:
+ %i3 = call float @llvm.fabs.f32(float undef) #0
+ %i4 = fcmp fast ult float %i3, 0x3FEFF7CEE0000000
+ br i1 %i4, label %bb5, label %bb6
+
+bb5:
+ unreachable
+
+bb6:
+ unreachable
+}
+
+declare float @llvm.fabs.f32(float) #0
+
+attributes #0 = { nounwind readnone speculatable willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir b/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
new file mode 100644
index 000000000000..d66b22dd33e0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
@@ -0,0 +1,56 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: undef_and_operand_to_bitset0
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: undef_and_operand_to_bitset0
+ ; CHECK: renamable $sgpr4 = S_BITSET0_B32 31, undef $sgpr4, implicit-def dead $scc
+ ; CHECK: S_ENDPGM 0, implicit $sgpr4
+ renamable $sgpr4 = S_AND_B32 undef renamable $sgpr4, 2147483647, implicit-def dead $scc
+ S_ENDPGM 0, implicit $sgpr4
+
+...
+
+---
+name: undef_or_operand_to_orn2
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: undef_or_operand_to_orn2
+ ; CHECK: renamable $sgpr4 = S_ORN2_B32 undef renamable $sgpr4, 16, implicit-def dead $scc
+ ; CHECK: S_ENDPGM 0, implicit $sgpr4
+ renamable $sgpr4 = S_OR_B32 undef renamable $sgpr4, -17, implicit-def dead $scc
+ S_ENDPGM 0, implicit $sgpr4
+
+...
+
+---
+name: undef_xor_operand_to_orn2
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: undef_xor_operand_to_orn2
+ ; CHECK: renamable $sgpr4 = S_XNOR_B32 undef renamable $sgpr4, 16, implicit-def dead $scc
+ ; CHECK: S_ENDPGM 0, implicit $sgpr4
+ renamable $sgpr4 = S_XOR_B32 undef renamable $sgpr4, -17, implicit-def dead $scc
+ S_ENDPGM 0, implicit $sgpr4
+
+...
+
+---
+name: kill_and_operand_to_bitset0
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr4
+ ; CHECK-LABEL: name: kill_and_operand_to_bitset0
+ ; CHECK: liveins: $sgpr4
+ ; CHECK: renamable $sgpr4 = S_BITSET0_B32 31, killed $sgpr4, implicit-def dead $scc
+ ; CHECK: S_ENDPGM 0, implicit $sgpr4
+ renamable $sgpr4 = S_AND_B32 killed renamable $sgpr4, 2147483647, implicit-def dead $scc
+ S_ENDPGM 0, implicit $sgpr4
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-insts-undef-reg-verifier-error.ll b/llvm/test/CodeGen/AMDGPU/shrink-insts-undef-reg-verifier-error.ll
new file mode 100644
index 000000000000..7e6e3f7d6930
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/shrink-insts-undef-reg-verifier-error.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s
+
+define void @bitset_verifier_error() local_unnamed_addr #0 {
+bb:
+ %i = call float @llvm.fabs.f32(float undef) #0
+ %i1 = bitcast float %i to i32
+ br label %bb2
+
+bb2: ; preds = %bb
+ %i3 = call float @llvm.fabs.f32(float undef) #0
+ %i4 = fcmp fast ult float %i3, 0x3FEFF7CEE0000000
+ br i1 %i4, label %bb5, label %bb6
+
+bb5: ; preds = %bb2
+ unreachable
+
+bb6: ; preds = %bb2
+ unreachable
+}
+
+
+declare float @llvm.fabs.f32(float) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone speculatable willreturn }
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