[PATCH] D85234: [AMDGPU] Scavenge a temp register for AGPR spill in fast RA

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D85234#2194434 <https://reviews.llvm.org/D85234#2194434>, @rampitec wrote:

> AFAIR another reason to request a vreg was that eliminateFrameIndex() does not always have a scavenger available.

Yes, but that's under target control. Having AGPRs could be another condition we could add to enable the scavenger. The alternative without the scavenger is to reserve a register. In this case since it's just a VGPR, the worst case is the emergency stack slot will be used for a temporary spill which as at least more sane than in the SGPR spilling case


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