[PATCH] D85234: [AMDGPU] Scavenge a temp register for AGPR spill in fast RA

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:1350
+    // deal with newly added virtual registers.
+    if (MF->getTarget().getOptLevel() == CodeGenOpt::None) {
+      std::unique_ptr<RegScavenger> RS(new RegScavenger());
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arsenm wrote:
> This is also assuming the allocator. Nothing like this should be based on the opt level
Any ideas how to check which allocator we use?


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:1361
+      MachineRegisterInfo &MRI = MF->getRegInfo();
+      Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    }
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arsenm wrote:
> I think this should be dealt with in eliminateFrameIndex rather than trying to speculatively add the def here
It seems more robust to use the allocator rather than scavenger. We may need scavenger at -O0, but at least can do it better at a normal opt level.


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  https://reviews.llvm.org/D85234/new/

https://reviews.llvm.org/D85234