[PATCH] D85234: [AMDGPU] Scavenge a temp register for AGPR spill in fast RA

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:1350
+    // deal with newly added virtual registers.
+    if (MF->getTarget().getOptLevel() == CodeGenOpt::None) {
+      std::unique_ptr<RegScavenger> RS(new RegScavenger());
----------------
This is also assuming the allocator. Nothing like this should be based on the opt level


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:1493-1494
+      std::unique_ptr<RegScavenger> RS(new RegScavenger());
+      RS->enterBasicBlock(MBB);
+      RS->skipTo(MI);
+      Tmp = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI,
----------------
This should enter block backwards


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85234/new/

https://reviews.llvm.org/D85234