[llvm] 8f65c93 - GlobalISel: Fix redundant variable and shadowing
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 4 19:22:07 PDT 2020
Author: Matt Arsenault
Date: 2020-08-04T22:03:55-04:00
New Revision: 8f65c933c42879ff807e3518d9f84892babd30a5
URL: https://github.com/llvm/llvm-project/commit/8f65c933c42879ff807e3518d9f84892babd30a5
DIFF: https://github.com/llvm/llvm-project/commit/8f65c933c42879ff807e3518d9f84892babd30a5.diff
LOG: GlobalISel: Fix redundant variable and shadowing
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index f914b0b26e4a..e7f105f1dfea 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -921,7 +921,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
case TargetOpcode::G_INSERT:
return narrowScalarInsert(MI, TypeIdx, NarrowTy);
case TargetOpcode::G_LOAD: {
- const auto &MMO = **MI.memoperands_begin();
+ auto &MMO = **MI.memoperands_begin();
Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
if (DstTy.isVector())
@@ -929,7 +929,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
- auto &MMO = **MI.memoperands_begin();
MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO);
MIRBuilder.buildAnyExt(DstReg, TmpReg);
MI.eraseFromParent();
More information about the llvm-commits
mailing list