[PATCH] D84359: [PowerPC] Add vector pair load/store instructions and vector pair register class

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:605
 
+def PPCRegVSRpRCAsmOperand : AsmOperandClass {
+  let Name = "RegVSRpRC"; let PredicateMethod = "isVSRpEvenRegNumber";
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Minor nit, but I am thinking it may be better to put the class definitions above the definitions of the predicates.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84359/new/

https://reviews.llvm.org/D84359