[PATCH] D83216: [Intrinsic] Add sshl.sat/ushl.sat, saturated shift intrinsics.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Still no replies to RFC thread :/



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Comment at: llvm/test/CodeGen/X86/sshl_sat.ll:11
+declare  i64 @llvm.sshl.sat.i64  (i64, i64)
+declare  <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
+
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It is best to put vector tests into a separate file from the getgo
See e.g. `uadd_sat_vec.ll`


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Comment at: llvm/test/CodeGen/X86/ushl_sat.ll:7
+declare  i15 @llvm.ushl.sat.i15  (i15, i15)
+declare  i16 @llvm.ushl.sat.i16  (i16, i16)
+declare  i18 @llvm.ushl.sat.i18  (i18, i18)
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It seems i8 is the only "basic" bit width missing.
It would probably good to have it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D83216/new/

https://reviews.llvm.org/D83216