[llvm] 23adbac - [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel.

[Cameron McInally via llvm-commits]

Author: Cameron McInally
Date: 2020-08-04T11:27:09-05:00
New Revision: 23adbac9ee23c10976e40c80999abf02ecb389b7

URL: https://github.com/llvm/llvm-project/commit/23adbac9ee23c10976e40c80999abf02ecb389b7
DIFF: https://github.com/llvm/llvm-project/commit/23adbac9ee23c10976e40c80999abf02ecb389b7.diff

LOG: [GlobalISel] Don't transform FSUB(-0, X) -> FNEG(X) in GlobalISel.

This patch stops unconditionally transforming FSUB(-0, X) into an FNEG(X) while building the MIR.

This corresponds with the SelectionDAGISel change in D84056.

Differential Revision: https://reviews.llvm.org/D85139

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
    llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
index 928743a6cbd7..b4ad3c5a2d48 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
@@ -353,8 +353,6 @@ class IRTranslator : public MachineFunctionPass {
   /// \pre \p U is a return instruction.
   bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
 
-  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
-
   bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
 
   bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
@@ -439,6 +437,9 @@ class IRTranslator : public MachineFunctionPass {
   bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
   }
+  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
+    return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
+  }
   bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
     return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
   }

diff  --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index b14492ce0123..be669eca0f6f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -294,24 +294,6 @@ bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
   return true;
 }
 
-bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
-  // -0.0 - X --> G_FNEG
-  if (isa<Constant>(U.getOperand(0)) &&
-      U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
-    Register Op1 = getOrCreateVReg(*U.getOperand(1));
-    Register Res = getOrCreateVReg(U);
-    uint16_t Flags = 0;
-    if (isa<Instruction>(U)) {
-      const Instruction &I = cast<Instruction>(U);
-      Flags = MachineInstr::copyFlagsFromInstruction(I);
-    }
-    // Negate the last operand of the FSUB
-    MIRBuilder.buildFNeg(Res, Op1, Flags);
-    return true;
-  }
-  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
-}
-
 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
   Register Op0 = getOrCreateVReg(*U.getOperand(0));
   Register Res = getOrCreateVReg(U);

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 11ffacae7b86..0d75894a81dc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1507,7 +1507,7 @@ define float @test_fneg_f32(float %x) {
 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FNEG [[ARG]]
 ; CHECK: $s0 = COPY [[RES]](s32)
-  %neg = fsub float -0.000000e+00, %x
+  %neg = fneg float %x
   ret float %neg
 }
 
@@ -1516,7 +1516,7 @@ define float @test_fneg_f32_fmf(float %x) {
 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $s0
 ; CHECK: [[RES:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
 ; CHECK: $s0 = COPY [[RES]](s32)
-  %neg = fsub fast float -0.000000e+00, %x
+  %neg = fneg fast float %x
   ret float %neg
 }
 
@@ -1525,7 +1525,7 @@ define double @test_fneg_f64(double %x) {
 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
 ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_FNEG [[ARG]]
 ; CHECK: $d0 = COPY [[RES]](s64)
-  %neg = fsub double -0.000000e+00, %x
+  %neg = fneg double %x
   ret double %neg
 }
 
@@ -1534,7 +1534,7 @@ define double @test_fneg_f64_fmf(double %x) {
 ; CHECK: [[ARG:%[0-9]+]]:_(s64) = COPY $d0
 ; CHECK: [[RES:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FNEG [[ARG]]
 ; CHECK: $d0 = COPY [[RES]](s64)
-  %neg = fsub fast double -0.000000e+00, %x
+  %neg = fneg fast double %x
   ret double %neg
 }