[PATCH] D85117: [SVE] Add lowering for fixed length vector and, or & xor operations.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

Thanks @cameron.mcinally.  Yes immAllOnesV is similar to what I'm after but I didn't want to restrict it to the all-1s mask.  I had some success creating "any_frag" but then had to implement a bunch of combines and extra lowering which we loose when moving away from the unpredicated ISD nodes.  On reflection since SVE already supports most instruction formats when it comes to the logical operations I'm thinking this isn't really the patch to introduce "any_frag" so if it's OK I'd like to promote this patch as the correct way to handle these operations.


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  https://reviews.llvm.org/D85117/new/

https://reviews.llvm.org/D85117