[PATCH] D85203: TableGen/GlobalISel: Allow inst matcher to check multiple opcodes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dsanders, paquette, aemerson, aditya_nandakumar.
Herald added subscribers: kerbowa, rovka, nhaehnle, jvesely.
Herald added a project: LLVM.
arsenm requested review of this revision.
Herald added a subscriber: wdng.

This is to initially handleg immAllOnesV, which should match
G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be
used for other patterns cases that map to multiple G_* instructions,
such as G_ADD and G_PTR_ADD.


https://reviews.llvm.org/D85203

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
  llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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