[PATCH] D85201: AMDGPU/GlobalISel: Match andn2/orn2 for more types

[Matt Arsenault via Phabricator via llvm-commits]

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Unfortunately this ends up not working as expected on targets with
16-bit operations due to AMDGPUCodeGenPrepare's promotion of uniform
16-bit ops to i32.

      

The vector case annoyingly requires switching the checked opcode,
since constants for vectors aren't directly handled.

      

I also need to think more carefully about whether this is valid for i1.


https://reviews.llvm.org/D85201

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

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