[PATCH] D85149: [FastISel] Don't transform FSUB(-0, X) -> FNEG(X) in FastISel

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
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This patch stops unconditionally transforming FSUB(-0, X) into an FNEG(X) while building the instructions.

This corresponds with the SelectionDAGISel change in D84056 <https://reviews.llvm.org/D84056>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85149

Files:
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll
  llvm/test/CodeGen/X86/fast-isel-fneg.ll


Index: llvm/test/CodeGen/X86/fast-isel-fneg.ll
===================================================================
--- llvm/test/CodeGen/X86/fast-isel-fneg.ll
+++ llvm/test/CodeGen/X86/fast-isel-fneg.ll
@@ -24,7 +24,7 @@
 ; SSE2-NEXT:    movl %ebp, %esp
 ; SSE2-NEXT:    popl %ebp
 ; SSE2-NEXT:    retl
-  %y = fsub double -0.0, %x
+  %y = fneg double %x
   ret double %y
 }
 
@@ -45,7 +45,7 @@
 ; SSE2-NEXT:    flds (%esp)
 ; SSE2-NEXT:    popl %eax
 ; SSE2-NEXT:    retl
-  %y = fsub float -0.0, %x
+  %y = fneg float %x
   ret float %y
 }
 
@@ -69,7 +69,7 @@
 ; SSE2-NEXT:    movsd %xmm0, (%eax)
 ; SSE2-NEXT:    retl
   %a = load double, double* %x
-  %b = fsub double -0.0, %a
+  %b = fneg double %a
   store double %b, double* %y
   ret void
 }
@@ -95,7 +95,7 @@
 ; SSE2-NEXT:    movd %xmm0, (%eax)
 ; SSE2-NEXT:    retl
   %a = load float, float* %x
-  %b = fsub float -0.0, %a
+  %b = fneg float %a
   store float %b, float* %y
   ret void
 }
Index: llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll
===================================================================
--- llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll
+++ /dev/null
@@ -1,22 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=finalize-isel | FileCheck %s
-
-; Make sure we output the right kill flag for the xor conversion.
-
-define void @goo(double* %x, double* %y) nounwind {
-; CHECK: %[[REG2:.*]]:gr64 = COPY $rsi
-; CHECK-NEXT: %[[REG0:.*]]:gr64 = COPY $rdi
-; CHECK-NEXT: %[[REG1:.*]]:gr64 = COPY killed %[[REG0]]
-; CHECK-NEXT: %[[REG3:.*]]:gr64 = COPY killed %[[REG2]]
-; CHECK-NEXT: %[[REG10:.*]]:fr64 = MOVSDrm_alt %[[REG1]], 1, $noreg, 0, $noreg :: (load 8 from %ir.x)
-; CHECK-NEXT: %[[REG6:.*]]:gr64 = MOVSDto64rr killed %[[REG10]]
-; CHECK-NEXT: %[[REG7:.*]]:gr64 = MOV64ri -9223372036854775808
-; CHECK-NEXT: %[[REG8:.*]]:gr64 = XOR64rr killed %[[REG6]], killed %[[REG7]], implicit-def $eflags
-; CHECK-NEXT: %[[REG9:.*]]:fr64 = MOV64toSDrr killed %[[REG8]]
-; CHECK-NEXT: MOVSDmr %[[REG3]], 1, $noreg, 0, $noreg, killed %[[REG9]] :: (store 8 into %ir.y)
-; CHECK-NEXT: RETQ
-  %a = load double, double* %x
-  %b = fsub double -0.0, %a
-  store double %b, double* %y
-  ret void
-}
Index: llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1845,13 +1845,8 @@
     return selectBinaryOp(I, ISD::FADD);
   case Instruction::Sub:
     return selectBinaryOp(I, ISD::SUB);
-  case Instruction::FSub: {
-    // FNeg is currently represented in LLVM IR as a special case of FSub.
-    Value *X;
-    if (match(I, m_FNeg(m_Value(X))))
-       return selectFNeg(I, X);
+  case Instruction::FSub:
     return selectBinaryOp(I, ISD::FSUB);
-  }
   case Instruction::Mul:
     return selectBinaryOp(I, ISD::MUL);
   case Instruction::FMul:


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