[PATCH] D85128: [Prototype][SVE] Support arm_sve_vector_bits attribute

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Not going to write detailed review comments, but this looks like the right approach in general.

One high-level thing to consider: we could still decide that in IR generation, we want to represent VLSTs registers using scalable vector types, like the original patch did.  This would allow avoiding the awkward "bitcast" implementation.  That interacts with a relatively narrow slice of clang CodeGen, though; we could easily change it later without impacting the rest of the changes.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D85128/new/

https://reviews.llvm.org/D85128