[PATCH] D83667: [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz
Nicholas Guy via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 3 05:20:55 PDT 2020
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG18279a54b5d3: [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz (authored by NickGuy).
Changed prior to commit:
https://reviews.llvm.org/D83667?vs=282523&id=282594#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83667/new/
https://reviews.llvm.org/D83667
Files:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/test/CodeGen/Thumb2/constant-hoisting.ll
Index: llvm/test/CodeGen/Thumb2/constant-hoisting.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/constant-hoisting.ll
+++ llvm/test/CodeGen/Thumb2/constant-hoisting.ll
@@ -37,26 +37,25 @@
; CHECK-V7M: mov r2, r0
; CHECK-V7M-NEXT: ldr r0, .LCPI0_0
; CHECK-V7M-NEXT: cmp r2, #50
-; CHECK-V7M-NEXT: beq .LBB0_5
+; CHECK-V7M-NEXT: beq .LBB0_3
; CHECK-V7M-NEXT: cmp r2, #1
-; CHECK-V7M-NEXT: beq .LBB0_7
+; CHECK-V7M-NEXT: ittt eq
+; CHECK-V7M-NEXT: addeq r0, r1
+; CHECK-V7M-NEXT: addeq r0, #1
+; CHECK-V7M-NEXT: bxeq lr
; CHECK-V7M-NEXT: cmp r2, #30
-; CHECK-V7M-NEXT: beq .LBB0_8
-; CHECK-V7M-NEXT: cbnz r2, .LBB0_6
+; CHECK-V7M-NEXT: ittt eq
+; CHECK-V7M-NEXT: addeq r0, r1
+; CHECK-V7M-NEXT: addeq r0, #2
+; CHECK-V7M-NEXT: bxeq lr
+; CHECK-V7M-NEXT: cbnz r2, .LBB0_4
+; CHECK-V7M-NEXT: .LBB0_2:
; CHECK-V7M-NEXT: add r0, r1
; CHECK-V7M-NEXT: bx lr
-; CHECK-V7M-NEXT: .LBB0_5:
+; CHECK-V7M-NEXT: .LBB0_3:
; CHECK-V7M-NEXT: add r0, r1
; CHECK-V7M-NEXT: adds r0, #4
-; CHECK-V7M-NEXT: .LBB0_6:
-; CHECK-V7M-NEXT: bx lr
-; CHECK-V7M-NEXT: .LBB0_7:
-; CHECK-V7M-NEXT: add r0, r1
-; CHECK-V7M-NEXT: adds r0, #1
-; CHECK-V7M-NEXT: bx lr
-; CHECK-V7M-NEXT: .LBB0_8:
-; CHECK-V7M-NEXT: add r0, r1
-; CHECK-V7M-NEXT: adds r0, #2
+; CHECK-V7M-NEXT: .LBB0_4:
; CHECK-V7M-NEXT: bx lr
; CHECK-V7M-NEXT: .p2align 2
; CHECK-V7M-NEXT: .LCPI0_0:
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -587,6 +587,13 @@
const MachineOperand &MO = MI.getOperand(i);
if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
(MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
+
+ // Filter out T1 instructions that have a dead CPSR,
+ // allowing IT blocks to be generated containing T1 instructions
+ const MCInstrDesc &MCID = MI.getDesc();
+ if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead())
+ continue;
+
Pred.push_back(MO);
Found = true;
}
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